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| 1/96 tspc860 preliminary specification beta site august 2000 features powerpc single issue integer core. precise exception model. extensive system development support - on-chip watchpoints and breakpoints, - program flow tracking, - on-chip emulation (once) development interface. high performance (dhrystone 2.1: 52 mips @ 50 mhz, 3.3v, 1.3 watts total power). low power (< 241 mw @25 mhz, 2.4 v internal, 3.3 v i/o-core, caches, mmus, i/o). mpc8xx powerpc system interface, including a periodic interrupt timer, a bus monitor, and real-time clocks. single issue, 32-bit version of the embedded powerpc core (fully compatible with book 1 of the powerpc architecture definition) with 32 x 32 bit fixed point registers embedded powerpc performs branch folding, branch prediction with conditional prefetch, without conditional execution 4 kbyte data cache and 4 kbyte instruction cache, each with an mmu instruction and data caches are two way, set associative, physical address, 4 word line burst, least recently used (lru) replacement, lockable on-line granularity mmus with 32 entry tlb, fully associative instruction and data tlbs mmus support multiple page sizes of 4kb, 16 kb, 256 kb, 512 kb and 8 mb ; 16 virtual address spaces and 8 protection groups advanced on-chip-emulation debug mode up to 32-bit data bus (dynamic bus sizing for 8 and 16 bits). 32 address lines fully static design. v cc = +3.3 v 5 % . f max = 66 mhz (80 mhz tbc) military temperature range : 55 c < t c < +125 c. p d = 0.75 w typical @ 66 mhz atm sar support available on tspc860sr version description the tspc860 powerpc quad integrated communication controller ( power quicc ) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. it particularly excels in communications and networking sys- tems. the power quicc (pronounced oquicko) can be described as a powerpc-based derivative of ts68en360 (quicc ). the cpu on the tspc860 is a 32-bit powerpc implementation that incorporates memory man- agement units (mmus) and instruction and data caches. the communications processor module (cpm) of the ts68en360 quicc has been enhanced with the addition of the interprocessor-inte- grated controller (i 2 c) channel. moderate to high digital signal processing (dsp) functionality has been added to the cpm. the memory controller has been enhanced, enabling the tspc860 to support any type of memory, including high performance memories and newer dynamic random access memories (drams). overall system functionality is completed with the addition of a pcmcia socket controller supporting up to two sockets and a real-time clock. pbga 357 zp suffix screening / quality this product will be manufactured in full compliance with : or according to atmel-grenoble standard. 32 bit quad integrate d power quicc tm communication controller
2/96 tspc860 summary 0&78.( &00 6.) 66&= #=78*1 97 #.,2&07 (8.:* 900?94 9++*67 28*62&0 900?%4 &2) 900?3;2 "*7.78367 "*(311*2)*) &7.( .2 322*(8.327 "*7*8 32+.,96&8.32 "*7*8 32+.,96&8.32 $ &2) *'9, 3687 %297*) 24987 %297*) 984987 #.,2&0 #8&8*7 )96.2, &6);&6* "*7*8 *2*6&0 *7.,2 &2) (327869(8.32 $*61.2&0 (322*(8.327 *&) 1&8*6.&0 &2) +.2.7- &(/&,* '73098* 1&<.191 6&8.2,7 $-*61&0 -&6&(8*6.78.(7 &6/.2, *2*6&0 6*59.6*1*287 0*(86.(&0 #4*(.+.(&8.327 0*(86.(&0 #4*(.+.(&8.327 328630 $.1.2, $" # $ # 0*(86.(&0 #4*(.+.(&8.327 3286300*6 0*(86.(&0 #4*(.+.(&8.327 &9) "&8* *2*6&836 0*(86.(&0 #4*(.+.(&8.327 $.1*6 0*(86.(&0 #4*(.+.(&8.327 #*6.&0 28*6+&(* 0*(86.(&0 #4*(.+.(&8.327 # 2 # 3)*@<8*62&0 03(/ 0*(86.(&0 #4*(.+.(&8.327 # 2 # 3)*@28*62&0 03(/ 0*(86.(&0 #4*(.+.(&8.327 8-*62*8 0*(86.(&0 #4*(.+.(&8.327 0*(86.(&0 #4*(.+.(&8.327@# > # &78*6 0*(86.(&0 #4*(.+.(&8.327 # #0&:* 0*(86.(&0 #4*(.+.(&8.327 0*(86.(&0 #4*(.+.(&8.327@# > 0*(86.(&0 #4*(.+.(&8.327@# > " &(/&,.2, *68.+.(&8* 3+ (3140.&2(* ! " 1'*))*) 3;*6 36* #=78*1 28*6+&(* %2.8 #% 3286300*6 3;*6 &2&,*1*28 31192.(&8.327 63(*7736 3)90* #3+8;&6* 314&8.'.0.8= 779*7 $# 3;*6!% 09*0*77 #=78*1 *7.,2 0&78.( &00 6.) 66&= tspc860 3/96 a. general description the tspc860 is functionally composed of three major blocks : a 32-bit powerpc core with mmus and caches a system interface unit a communications processor module figure 1 : block diagram view of the tspc860 1. main features the following is a list of the tspc860's important features: fully static design four major power saving modes 357 ompac ball grid array packaging (plastic) 32-bit address and data busses flexible memory management 4-kbyte physical address, two-way, set-associative data cache 4-kbyte physical address, two-way, set-associative instruction cache eight-bank memory controller - glueless interface to sram, dram, eprom, flash and other peripherals - byte write enables and selectable parity generation - 32-bit address decodes with bit masks 4/96 tspc860 system interface unit- - clock synthesizer- - power management- - reset controller- - powerpc decrementer and time base- - real-time clock register- - periodic interrupt timer- - hardware bus monitor and software watchdog timer- - ieee 1149.1 jtag test access port communications processor module - embedded 32-bit risc controller architecture for flexible i/o - interfaces to powerpc core through on-chip dual-port ram and virtual dma channel controller - continuous mode transmission and reception on all serial channels - serial dma channels for reception and transmission on all serial channels - i/o registers with open-drain and interrupt capability - memory-memory and memory-i/o transfers with virtual dma functionality - protocols supported by rom or downloadable microcode and include, but limited to, the digital portion of : ethernet / ieee 802.3 cs/cdma hdlc2 / sdlc and hdlc bus apple talk signaling system #7 (ram microcode only) universal asynchronous receiver transmitter (uart) synchronous uart binary synchronous (bisync) communications totally transparent totally transparent with crc profibus (ram microcode option) asynchronous hdlc ddcmp v.14 (ram microcode option) x.21 (ram microcode option) v.32bis datapump filters irda serial infrared basis rate isdn (bri) in conjunction with smc channels primary rate isdn (mh version only) - four hardware serial communications controller channels supporting the protocols - two hardware serial management channels management for bri devices as general circuit interface controller multiplexed channels low-speed uart operation - hardware serial peripheral interfaces -i 2 c (microwire compatible) interface - time-slot assigner - port supports centronics interfaces anc chip-to-chip - four independent baud rate generators and four input clock pins for supplying clocks to smc and scc serial channels - four independant 16-bit timers which can be interconnected as two 32-bit timers tspc860 5/96 2. pin assignement 2.1. plastic ball grid array top view figure 2 : pin assignment 3. signals description this section describes the signals on the tspc860. 6/96 tspc860 tspc860 figure 3 : tspc860 external signals tspc860 7/96 tspc860 figure 4 : tspc860 signals and pin numbers (part 1) 8/96 tspc860 tspc860 figure 5 : tspc860 signals and pin numbers (part 2) tspc860 9/96 3.1. system bus signals the tspc860 system bus consists of all signals that interface with the external bus. many of these signals perform different fu nctions, depending on how the user assigns them. the following input and output signals are identified by their abbreviation. each signa l's pin number can be found in figure 4 and figure 5. table 10. signal descriptions name reset number type description a(031) hi-z see figure 5 bidirectional three-state address busprovides the address for the current bus cycle. a0 is the most-significant signal. the bus is output when an internal master starts a transaction on the external bus. the bus is input when an external master starts a transaction on the bus. tsiz0 reg hi-z b9 bidirectional three-state transfer size 0when accessing a slave in the external bus, used (together with tsiz1) by the bus master to indicate the number of operand bytes waiting to be transferred in the current bus cycle. tsiz0 is an input when an external master starts a bus transaction. registerwhen an internal master initiates an access to a slave controlled by the pcmcia interface, reg is output to indicate which space in the pcmcia card is accessed. tsiz1 hi-z c9 bidirectional three-state transfer size 1used (with tsiz0) by the bus master to indicate the number of operand bytes waiting to be transferred in the current bus cycle. the tspc860 drives tsiz1 when it is bus master. tsiz1 is input when an external master starts a bus transaction. rd/wr hi-z b2 bidirectional three-state read/writedriven by the bus master to indicate the direction of the bus's data transfer. a logic one indicates a read from a slave device and a logic zero indicates a write to a slave device. the tspc860 drives this signal when it is bus master. input when an external master initiates a transaction on the bus. burst hi-z f1 bidirectional three-state burst transactiondriven by the bus master to indicate that the current initiated transfer is a burst. the tspc860 drives this signal when it is bus master. this signal is input when an external master initiates a transaction on the bus. bdip gpl_b 5 see section 1.5 d2 bidirectional three-state burst data in progresswhen accessing a slave device in the external bus, the master on the bus asserts this signal to indicate that the data beat in front of the current one is the one requested by the master. bdip is negated before the expected last data beat of the burst transfer. general-purpose line b5used by the memory controller when upmb takes control of the slave access. ts hi-z f3 bidirectional active pull-up transfer startasserted by the bus master to indicate the start of a bus cycle that transfers data to or from a slave device. driven by the master only when it has gained the ownership of the bus. every master should negate this signal before the bus relinquish. ts requires the use of an external pull-up resistor. the tspc860 samples ts when it is not the external bus master to allow the memory controller/pcmcia interface to control the accessed slave device. it indicates that an external synchronous master initiated a transaction. 10/96 tspc860 table 10. signal descriptions name description type number reset ta hi-z c2 bidirectional active pull-up transfer acknowledgeindicates that the slave device addressed in the current transaction accepted data sent by the master (write) or has driven the data bus with valid data (read). this is an output when the pcmcia interface or memory controller controls the transaction. the only exception occurs when the memory controller controls the slave access by means of the gpcm and the corresponding option register is instructed to wait for an external assertion of ta . every slave device should negate ta after a transaction ends and immediately three-state it to avoid bus contention if a new transfer is initiated addressing other slave devices. ta requires the use of an external pull-up resistor. tea hi-z d1 open-drain transfer error acknowledgeindicates that a bus error occurred in the current transaction. the tspc860 asserts tea when the bus monitor does not detect a bus cycle termination within a reasonable amount of time. asserting tea terminates the bus cycle, thus ignoring the state of ta . tea requires the use of an external pull-up resistor. bi hi-z e3 bidirectional active pull-up burst inhibitindicates that the slave device addressed in the current burst transaction cannot support burst transfers. it acts as an output when the pcmcia interface or the memory controller takes control of the transaction. bi requires the use of an external pull-up resistor. rsv irq2 see section 1.5 h3 bidirectional three-state reservationthe tspc860 outputs this three-state signal in conjunction with the address bus to indicate that the core initiated a transfer as a result of a stwcx . or lwarx . interrupt request 2one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. kr /retry irq4 spkrout see section 1.5 k1 bidirectional three-state kill reservationthis input is used as a part of the memory reservation protocol, when the tspc860 initiated a transaction as the result of a stwcx . instruction. retrythis input is used by a slave device to indicate it cannot accept the transaction. the tspc860 must relinquish mastership and reinitiate the transaction after winning in the bus arbitration. interrupt request 4. one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal that is sent to the interrupt controller is the logical and of this line (if defined as irq4 ) and dp1/irq4 (if defined as irq4 ). spkroutdigital audio wave form output to be driven to the system speaker. cr irq3 hi-z f2 input cancel reservationthis input is used as a part of the storage reservation protocol. interrupt request 3one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal sent to the interrupt controller is the logical and of cr /irq3 (if defined as irq3 ) and dp0/irq3 if defined as irq3 . tspc860 11/96 table 10. signal descriptions name description type number reset d(031) hi-z(pulled low if rstconf pulled down) see figure 5 bidirectional three-state data busthis bidirectional three-state bus provides the general-purpose data path between the tspc860 and all other devices. the 32-bit data path can be dynamically sized to support 8-, 16-, or 32-bit transfers. d0 is the msb of the data bus. dp0 irq3 hi-z v3 bidirectional threestate data parity 0provides parity generation and checking for d(07) for transfers to a slave device initiated by the tspc860. the parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves sitting on the external bus. parity generation and checking is not supported for external masters. interrupt request 3one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal sent to the interrupt controller is the logical and of dp0/irq3 (if defined as irq3 ) and cr /irq3 (if defined as irq3 ). dp1 irq4 hiz v5 bidirectional threestate data parity 1provides parity generation and checking for d(815) for transfers to a slave device initiated by the tspc860. the parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. parity generation and checking is not supported for external masters. interrupt request 4one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal sent to the interrupt controller is the logical and of this line (if defined as irq4 ) and kr /irq4 /spkrout (if defined as irq4 ). dp2 irq5 hiz w4 bidirectional threestate data parity 2provides parity generation and checking for d(1623) for transfers to a slave device initiated by the tspc860. the parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. parity generation and checking is not supported for external masters. interrupt request 5one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. dp3 irq6 hiz v4 bidirectional threestate data parity 3provides parity generation and checking for d(2431) for transfers to a slave device initiated by the tspc860. the parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. parity generation and checking is not supported for external masters. interrupt request 6one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal sent to the interrupt controller is the logical and of this line (if defined as irq6 ) and the frz/irq6 (if defined as irq6 ). 12/96 tspc860 table 10. signal descriptions name description type number reset br hiz g4 bidirectional bus requestasserted low when a possible master is requesting ownership of the bus. when the tspc860 is configured to work with the internal arbiter, this signal is configured as an input. when the tspc860 is configured to work with an external arbiter, this signal is configured as an output and asserted every time a new transaction is intended to be initiated (no parking on the bus). bg hiz e2 bidirectional bus grantasserted low when the arbiter of the external bus grants the bus to a specific device. when the tspc860 is configured to work with the internal arbiter, bg is configured as an output and asserted every time the external master asserts br and its priority request is higher than any internal sources requiring a bus transfer. however, when the tspc860 is configured to work with an external arbiter, bg is an input. bb hiz e1 bidirectional active pullup bus busyasserted low by a master to show that it owns the bus. the tspc860 asserts bb after the arbiter grants it bus ownership and bb is negated. frz irq6 see section 1.5 g3 bidirectional freezeoutput asserted to indicate that the core is in debug mode. interrupt request 6one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. note that the interrupt request signal sent to the interrupt controller is the logical and of frz/irq6 (if defined as irq6 ) and dp3/irq6 (if defined as irq6 ). irq0 hiz v14 input interrupt request 0one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. irq1 hiz u14 input interrupt request 1one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. irq7 hiz w15 input interrupt request 7one of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. cs (05) high c3, a2, d4, e4, a4, b4 output chip selectthese outputs enable peripheral or memory devices at programmed addresses if they are appropriately defined. cs0 can be configured to be the global chipselect for the boot device. cs6 ce1_b high d5 output chip select 6this output enables a peripheral or memory device at a programmed address if defined appropriately in the br6 and or6 in the memory controller. card enable 1 slot bthis output enables even byte transfers when accesses to the pcmcia slot b are handled under the control of the pcmcia interface. tspc860 13/96 table 10. signal descriptions name description type number reset cs7 ce2_b high c4 output chip select 7this output enables a peripheral or memory device at a programmed address if defined appropriately in the br7 and or7 in the memory controller. card enable 2 slot bthis output enables odd byte transfers when accesses to the pcmcia slot b are handled under the control of the pcmcia interface. we0 bs_b0 iord high c7 output write enable 0output asserted when a write access to an external slave controlled by the gpcm is initiated by the tspc860. we0 is asserted if d(07) contains valid data to be stored by the slave device. byte select 0 on upmboutput asserted under control of the upmb, as programmed by the user. in a read or write transfer, the line is only asserted if d(07) contains valid data. io device readoutput asserted when the tspc860 starts a read access to a region controlled by the pcmcia interface. asserted only for accesses to a pc card i/o space. we1 bs_b1 iowr high a6 output write enable 1output asserted when the tspc860 initiates a write access to an external slave controlled by the gpcm. we1 is asserted if d(815) contains valid data to be stored by the slave device. byte select 1 on upmboutput asserted under control of the upmb, as programmed by the user. in a read or write transfer, the line is only asserted if d(815) contains valid data. i/o device writethis output is asserted when the tspc860 initiates a write access to a region controlled by the pcmcia interface. iowr is asserted only if the access is to a pc card i/o space. we2 bs_b2 pcoe high b6 output write enable 2output asserted when the tspc860 starts a write access to an external slave controlled by the gpcm. we2 is asserted if d(1623) contains valid data to be stored by the slave device. byte select 2 on upmboutput asserted under control of the upmb, as programmed by the user. in a read or write transfer, bs_b2 is asserted only d(1623) contains valid data. pcmcia output enableoutput asserted when the tspc860 initiates a read access to a memory region under the control of the pcmcia interface. we3 bs_b3 pcwe high a5 output write enable 3output asserted when the tspc860 initiates a write access to an external slave controlled by the gpcm. we3 is asserted if d(2431) contains valid data to be stored by the slave device. byte select 3 on upmboutput asserted under control of the upmb, as programmed by the user. in a read or write transfer, bs_b3 is asserted only if d(2431) contains valid data. pcmcia write enableoutput asserted when the tspc860 initiates a write access to a memory region under control of the pcmcia interface. 14/96 tspc860 table 10. signal descriptions name description type number reset bs_a (03) high d8, c8, a7, b8 output byte select 0 to 3 on upmaoutputs asserted under requirement of the upmb, as programmed by the user. for read or writes, asserted only if their corresponding data lanes contain valid data: bs_a0 for d(07), bs_a1 for d(815), bs_a2 for d(1623), bs_a3 for d(2431) gpl_a0 gpl_b0 high d7 output generalpurpose line 0 on upmathis output reflects the value specified in the upma when an external transfer to a slave is controlled by the upma. generalpurpose line 0 on upmbthis output reflects the value specified in the upmb when an external transfer to a slave is controlled by the upmb. oe gpl_a1 gpl_b1 high c6 output output enableoutput asserted when the tspc860 initiates a read access to an external slave controlled by the gpcm. generalpurpose line 1on upmathis output reflects the value specified in the upma when an external transfer to a slave is controlled by upma. generalpurpose line 1 on upmbthis output reflects the value specified in the upmb when an external transfer to a slave is controlled by upmb. gpl_a (23) gpl_b (23) cs (23) high b5, c5 output generalpurpose line 2 and 3 on upmathese outputs reflect the value specified in the upma when an external transfer to a slave is controlled by upma. generalpurpose line 2 and 3 on upmbthese outputs reflect the value specified in the upmb when an external transfer to a slave is controlled by upmb. chip select 2 and 3these outputs enable peripheral or memory devices at programmed addresses if they are appropriately defined. the double drive capability for cs2 and cs3 is independently defined for each signal in the siumcr. upwaita gpl_a4 hiz c1 bidirectional user programmable machine wait athis input is sampled as defined by the user when an access to an external slave is controlled by the upma. generalpurpose line 4 on upmathis output reflects the value specified in the upma when an external transfer to a slave is controlled by upma. upwaitb gpl_b 4 hiz b1 bidirectional user programmable machine wait bthis input is sampled as defined by the user when an access to an external slave is controlled by the upmb. generalpurpose line 4 on upmbthis output reflects the value specified in the upmb when an external transfer to a slave is controlled by upmb. gpl_a5 high d3 output generalpurpose line 5 on upmathis output reflects the value specified in the upma when an external transfer to a slave is controlled by upma. this signal can also be controlled by the upmb. poreset hiz r2 input power on resetwhen asserted, this input causes the tspc860 to enter the poweron reset state. tspc860 15/96 table 10. signal descriptions name description type number reset rstconf hiz p3 input reset configurationthe tspc860 samples this input while hreset is asserted. if rstconf is asserted, the configuration mode is sampled in the form of the hard reset configuration word driven on the data bus. when rstconf is negated, the tspc860 uses the default configuration mode. note that the initial base address of internal registers is determined in this sequence. hreset low n4 opendrain hard resetasserting this open drain signal puts the tspc860 in hard reset state. sreset low p2 opendrain soft resetasserting this open drain line puts the tspc860 in soft reset state. xtal analog driving p1 analog output this output is one of the connections to an external crystal for the internal oscillator circuitry. extal hiz n1 analog input (3.3v only) this line is one of the connections to an external crystal for the internal oscillator circuitry. xfc analog driving t2 analog input external filter capacitancethis input is the connection pin for an external capacitor filter for the pll circuitry. clkout see note. (high until spll locked, then oscillating) w3 output clock outthis output is the clock system frequency. extclk hiz n2 input (3.3v only) external clockthis input is the external input clock from an external source. texp high n3 output timer expiredthis output reflects the status of plprcr[texps]. ale_a low k2 output address latch enable athis output is asserted when tspc860 initiates an access to a region under the control of the pcmcia interface to socket a. ce1_a high b3 output card enable 1 slot athis output enables even byte transfers when accesses to pcmcia slot a are handled under the control of the pcmcia interface. ce2_a high a3 output card enable 2 slot athis output enables odd byte transfers when accesses to pcmcia slot a are handled under the control of the pcmcia interface. wait_a hiz r3 input wait slot athis input, if asserted low, causes a delay in the completion of a transaction on the pcmcia controlled slot a. wait_b hiz r4 input wait slot bthis input, if asserted low, causes a delay in the completion of a transaction on the pcmcia controlled slot b. ip_a(01) hiz t5, t4 input input port a 01the tspc860 monitors these inputs that are reflected in the pipr and pscr of the pcmcia interface. 16/96 tspc860 table 10. signal descriptions name description type number reset ip_a2 iois16_a hiz u3 input input port a 2the tspc860 monitors these inputs; its value and changes are reported in the pipr and pscr of the pcmcia interface. i/o device a is 16 bits ports sizethe tspc860 monitors this input when a transaction under the control of the pcmcia interface is initiated to an i/o region in socket a of the pcmcia space. ip_a(37) hiz w2, u4, u5, t6, t3 input input port a 37ethe tspc860 monitors these inputs; their values and changes are reported in the pipr and pscr of the pcmcia interface. ale_b dsck/at1 see section 1.5 j1 bidirectional threestate address latch enable bthis output is asserted when the tspc860 initiates an access to a region under the control of the pcmcia socket b interface. development serial clockthis input is the clock for the debug port interface. address type 1the tspc860 drives this bidirectional threestate line when it initiates a transaction on the external bus. when the transaction is initiated by the core, it indicates if the transfer is for user or supervisor state. this signal is not used for transactions initiated by external masters. ip_b(01) iwp(01) vfls(01) see section 1.5 h2, j3 bidirectional input port b 01ethe tspc860 senses these inputs; their values and changes are reported in the pipr and pscr of the pcmcia interface. instruction watchpoint 01ethese outputs report the detection of an instruction watchpoint in the program flow executed by the core. visible history buffer flushes statusthe tspc860 outputs vfls(01) when program instruction flow tracking is required. they report the number of instructions flushed from the history buffer in the core. ip_b2 iois16_b at2 hiz j2 bidirectional threestate input port b 2the tspc860 senses this input; its value and changes are reported in the pipr and pscr of the pcmcia interface. i/o device b is 16 bits port sizethe tspc860 monitors this input when a pcmcia interface transaction is initiated to an i/o region in socket b in the pcmcia space. address type 2the tspc860 drives this bidirectional threestate signal when it initiates a transaction on the external bus. if the core initiates the transaction, it indicates if the transfer is instruction or data. this signal is not used for transactions initiated by external masters. ip_b3 iwp2 vf2 see section 1.5 g1 bidirectional input port b 3the tspc860 monitors this input; its value and changes are reported in the pipr and pscr of the pcmcia interface. instruction watchpoint 2this output reports the detection of an instruction watchpoint in the program flow executed by the core. visible instruction queue flush statusthe tspc860 outputs vf2 with vf0/vf1 when instruction flow tracking is required. vf n reports the number of instructions flushed from the instruction queue in the core. tspc860 17/96 table 10. signal descriptions name description type number reset ip_b4 lwp0 vf0 hiz g2 bidirectional input port b 4the tspc860 monitors this input; its value and changes are reported in the pipr and pscr of the pcmcia interface. load/store watchpoint 0this output reports the detection of a data watchpoint in the program flow executed by the core. visible instruction queue flushes statusthe tspc860 outputs vf0 with vf1/vf2 when instruction flow tracking is required. vf n reports the number of instructions flushed from the instruction queue in the core. ip_b5 lwp1 vf1 hiz j4 bidirectional input port b 5the tspc860 monitors this input; its value and changes are reported in the pipr and pscr of the pcmcia interface. load/store watchpoint 1this output reports the detection of a data watchpoint in the program flow executed by the core. visible instruction queue flushes statusthe tspc860 outputs vf1 with vf0 and vf2 when instruction flow tracking is required. vf n reports the number of instructions flushed from the instruction queue in the core. ip_b6 dsdi at0 hiz k3 bidirectional threestate input port b 6the tspc860 senses this input and its value and changes are reported in the pipr and pscr of the pcmcia interface. development serial data inputdata input for the debug port interface. address type 0the tspc860 drives this bidirectional threestate line when it initiates a transaction on the external bus. if high (1), the transaction is the cpm. if low (0), the transaction initiator is the cpu. this signal is not used for transactions initiated by external masters. ip_b7 ptr at3 hiz h1 bidirectional threestate input port b 7the tspc860 monitors this input; its value and changes are reported in the pipr and pscr of the pcmcia interface. program traceto allow program flow tracking, the tspc860 asserts this output to indicate an instruction fetch is taking place. address type 3the tspc860 drives the bidirectional threestate signal when it starts a transaction on the external bus. when the core initiates a transfer, at3 indicates whether it is a reservation for a data transfer or a program trace indication for an instruction fetch. this signal is not used for transactions initiated by external masters. op(01) low l4, l2 output output port 01ethe tspc860 generates these outputs as a result of a write to the pgcra register in the pcmcia interface. op2 modck1 sts hiz l1 bidirectional output port 2this output is generated by the tspc860 as a result of a write to the pgcrb register in the pcmcia interface. mode clock 1input sampled when poreset is negated to configure pll/clock mode. special transfer startthe tspc860 drives this output to indicate the start of an external bus transfer or of an internal transaction in showcycle mode. 18/96 tspc860 table 10. signal descriptions name description type number reset op3 modck2 dsdo hiz m4 bidirectional output port 3this output is generated by the tspc860 as a result of a write to the pgcrb register in the pcmcia interface. mode clock 2this input is sampled at the poreset negation to configure the pll/clock mode of operation. development serial data outputoutput data from the debug port interface. baddr30 reg hiz k4 output burst address 30this output duplicates the value of a30 when the following is true: ? an internal master in the tspc860 initiates a transaction on the external bus. ? an asynchronous external master initiates a transaction. ? a synchronous external master initiates a single beat transaction. the memory controller uses baddr30 to increment the address lines that connect to memory devices when a synchronous external master or an internal master initiates a burst transfer. registerwhen an internal master initiates an access to a slave under control of the pcmcia interface, this signal duplicates the value of tsiz0/reg . when an external master initiates an access, reg is output by the pcmcia interface (if it must handle the transfer) to indicate the space in the pcmcia card being accessed. baddr(282 9) hiz m3 m2 output burst addressoutputs that duplicate a(2829) values when one of the following occurs: ? an internal master in the tspc860 initiates a transaction on the external bus. ? an asynchronous external master initiates a transaction. ? a synchronous external master initiates a single beat transaction. the memory controller uses these signals to increment the address lines that connect to memory devices when a synchronous external or internal master starts a burst transfer. as hiz l3 input address strobeinput driven by an external asynchronous master to indicate a valid address on a(031). the tspc860 memory controller synchronizes as and controls the memory device addressed under its control. pa[15] rxd1 hiz c18 bidirectional generalpurpose i/o port a bit 15ebit 15 of the generalpurpose i/o port a. rxd1receive data input for scc1. pa[14] txd1 d17 bidirectional (optional: opendrain) generalpurpose i/o port a bit 14bit 14 of the generalpurpose i/o port a. txd1transmit data output for scc1. txd1 has an opendrain capability. pa[13] rxd2 e17 bidirectional generalpurpose i/o port a bit 13bit 13 of the generalpurpose i/o port a. rxd2receive data input for scc2. tspc860 19/96 table 10. signal descriptions name description type number reset pa[12] txd2 f17 bidirectional (optional: opendrain) generalpurpose i/o port a bit 12bit 12 of the generalpurpose i/o port a. txd2transmit data output for scc2. txd2 has an opendrain capability. pa[11] l1txdb g16 bidirectional (optional: opendrain) generalpurpose i/o port a bit 11bit 11 of the generalpurpose i/o port a. l1txdbtransmit data output for the serial interface tdm port b. l1txdb has an opendrain capability. pa[10] l1rxdb j17 bidirectional generalpurpose i/o port a bit 10bit 10 of the generalpurpose i/o port a. l1rxdbreceive data input for the serial interface tdm port b. pa[9] l1txda k18 bidirectional (optional: opendrain) generalpurpose i/o port a bit 11bit 9 of the generalpurpose i/o port a. l1txdatransmit data output for the serial interface tdm port a. l1txda has an opendrain capability. pa[8] l1rxda l17 bidirectional generalpurpose i/o port a bit 8bit 8 of the generalpurpose i/o port a. l1rxdareceive data input for the serial interface tdm port a. pa[7] clk1 tin1 l1rclka brgo1 m19 bidirectional generalpurpose i/o port a bit 7bit 7 of the generalpurpose i/o port a. clk1one of eight clock inputs that can be used to clock sccs and smcs. tin1timer 1 external clock. l1rclkareceive clock for the serial interface tdm port a. brgo1output clock of brg1. pa[6] clk2 tout1 brgclk1 m17 bidirectional generalpurpose i/o port a bit 6bit 6 of the generalpurpose i/o port a. clk2one of eight clock inputs that can be used to clock sccs and smcs. tout1 timer 1 output. brgclk1one of two external clock inputs of the brgs. pa[5] clk3 tin2 l1tclka brgo2 n18 bidirectional generalpurpose i/o port a bit 5bit 5 of the generalpurpose i/o port a. clk3one of eight clock inputs that can be used to clock sccs and smcs. tin2timer 2 external clock input. l1tclkatransmit clock for the serial interface tdm port a. brgo2output clock of brg2. pa[4] clk4 tout2 hiz p19 bidirectional generalpurpose i/o port a bit 4bit 4 of the generalpurpose i/o port a. clk4one of eight clock inputs that can be used to clock sccs and smcs. tout2 timer 2 output. 20/96 tspc860 table 10. signal descriptions name description type number reset pa[3] clk5 tin3 brgo3 p17 bidirectional generalpurpose i/o port a bit 3bit 3 of the generalpurpose i/o port a. clk5one of eight clock inputs that can be used to clock sccs and smcs. tin3timer 3 external clock input. brgo3output clock of brg3. pa[2] clk6 tout3 l1rclkb brgclk2 r18 bidirectional generalpurpose i/o port a bit 2bit 2 of the generalpurpose i/o port a. clk6one of eight clock inputs that can be used to clock the sccs and smcs. tout3 timer 3 output. l1rclkbreceive clock for the serial interface tdm port b. brgclk2one of the two external clock inputs of the brgs. pa[1] clk7 tin4 brgo4 t19 bidirectional generalpurpose i/o port a bit 1bit 1 of the generalpurpose i/o port a. clk7one of eight clock inputs that can be used to clock sccs and smcs. tin4timer 4 external clock input. brgo4brg4 output clock. pa[0] clk8 tout4 l1tclkb u19 bidirectional generalpurpose i/o port a bit 0bit 0 of the generalpurpose i/o port a. clk8one of eight clock inputs that can be used to clock sccs and smcs. tout4 timer 4 output. l1tclkbtransmit clock for the serial interface tdm port b. pb[31] spisel reject1 c17 bidirectional (optional: opendrain) generalpurpose i/o port b bit 31ebit 31 of the generalpurpose i/o port b. spisel spi slave select input. reject1 scc1 cam interface reject pin. pb[30] spiclk rstrt2 c19 bidirectional (optional: opendrain) generalpurpose i/o port b bit 30bit 30 of the generalpurpose i/o port b. spiclkspi output clock when it is configured as a master or spi input clock when it is configured as a slave. rstrt2 scc2 serial cam interface output signal that marks the start of a frame. pb[29] spimosi e16 bidirectional (optional: opendrain) generalpurpose i/o port b bit 29bit 29 of the generalpurpose i/o port b. spimosispi output data when it is configured as a master or spi input data when it is configured as a slave. pb[28] spimiso brgo4 d19 bidirectional (optional: opendrain) generalpurpose i/o port b bit 28bit 29 of the generalpurpose i/o port b. spimisospi input data when the tspc860 is a master; spi output data when it is a slave. brgo4brg4 output clock. tspc860 21/96 table 10. signal descriptions name description type number reset pb[27] i2csda brgo1 hiz e19 bidirectional (optional: opendrain) generalpurpose i/o port b bit 27bit 27 of the generalpurpose i/o port b. i2csdai 2 c serial data pin. bidirectional; should be configured as an opendrain output. brgo1brg1 output clock. pb[26] i2cscl brgo2 f19 bidirectional (optional: opendrain) generalpurpose i/o port b bit 26bit 26 of the generalpurpose i/o port b. i2cscli 2 c serial clock pin. bidirectional; should be configured as an opendrain output. brgo2brg2 output clock. pb[25] smtxd1 j16 bidirectional (optional: opendrain) generalpurpose i/o port b bit 25bit 25 of the generalpurpose i/o port b. smtxd1smc1 transmit data output. pb[24] smrxd1 j18 bidirectional (optional: opendrain) generalpurpose i/o port b bit 24bit 24 of the generalpurpose i/o port b. smrxd1smc1 receive data input. pb[23] smsyn1 sdack1 k17 bidirectional (optional: opendrain) generalpurpose i/o port b bit 23bit 23 of the generalpurpose i/o port b. smsyn1 smc1 external sync input. sdack1 sdma acknowledge 1 output that is used as a peripheral interface signal for idma emulation, or as a cam interface signal for ethernet. pb[22] smsyn2 sdack2 l19 bidirectional (optional: opendrain) generalpurpose i/o port b bit 22bit 22 of the generalpurpose i/o port b. smsyn2 smc2 external sync input. sdack2 sdma acknowledge 2 output that is used as a peripheral interface signal for idma emulation, or as a cam interface signal for ethernet. pb[21] smtxd2 l1clkob k16 bidirectional (optional: opendrain) generalpurpose i/o port b bit 21bit 21 of the generalpurpose i/o port b. smtxd2smc2 transmit data output. l1clkobclock output from the serial interface tdm port b. pb[20] smrxd2 l1clkoa l16 bidirectional (optional: opendrain) generalpurpose i/o port b bit 20bit 20 of the generalpurpose i/o port b. smrxd2smc2 receive data input. l1clkoaclock output from the serial interface tdm port a. pb[19] rts1 l1st1 n19 bidirectional (optional: opendrain) generalpurpose i/o port b bit 19bit 19 of the generalpurpose i/o port b. rts1 request to send modem line for scc1. l1st1one of four output strobes that can be generated by the serial interface. pb[18] rts2 l1st2 n17 bidirectional (optional: opendrain) generalpurpose i/o port b bit 18bit 18 of the generalpurpose i/o port b. rts2 request to send modem line for scc2. l1st2one of four output strobes that can be generated by the serial interface. 22/96 tspc860 table 10. signal descriptions name description type number reset pb[17] l1rqb l1st3 hiz p18 bidirectional (optional: opendrain) generalpurpose i/o port b bit 17bit 17 of the generalpurpose i/o port b. l1rqb dchannel request signal for the serial interface tdm port b. l1st3one of four output strobes that can be generated by the serial interface. pb[16] l1rqa l1st4 n16 bidirectional (optional: opendrain) generalpurpose i/o port b bit 16bit 16 of the generalpurpose i/o port b. l1rqa dchannel request signal for the serial interface tdm port a. l1st4one of four output strobes that can be generated by the serial interface. pb[15] brgo3 r17 bidirectional generalpurpose i/o port b bit 15bit 15 of the generalpurpose i/o port b. brgo3brg3 output clock. pb[14] rstrt1 u18 bidirectional generalpurpose i/o port b bit 14bit 14 of the generalpurpose i/o port b. rstrt1 scc1 serial cam interface outputs that marks the start of a frame. pc[15] dreq0 rts1 l1st1 d16 bidirectional generalpurpose i/o port c bit 15bit 15 of the generalpurpose i/o port c. dreq0 idma channel 0 request input. rts1 request to send modem line for scc1. l1st1one of four output strobes that can be generated by the serial interface. pc[14] dreq1 rts2 l1st2 d18 bidirectional generalpurpose i/o port c bit 14bit 14 of the generalpurpose i/o port c. dreq1 idma channel 1 request input. rts2 request to send modem line for scc2. l1st2one of four output strobes that can be generated by the serial interface. pc[13] l1rqb l1st3 e18 bidirectional generalpurpose i/o port c bit 13bit 13 of the generalpurpose i/o port c. l1rqb dchannel request signal for the serial interface tdm port b. l1st3one of four output strobes that can be generated by the serial interface. pc[12] l1rqa l1st4 f18 bidirectional generalpurpose i/o port c bit 12bit 12 of the generalpurpose i/o port c. l1rqa dchannel request signal for the serial interface tdm port a. l1st4one of four output strobes that can be generated by the serial interface. pc[11] cts1 j19 bidirectional generalpurpose i/o port c bit 11bit 11 of the generalpurpose i/o port c. cts1 clear to send modem line for scc1. tspc860 23/96 table 10. signal descriptions name description type number reset pc[10] cd1 tgate1 hiz k19 bidirectional generalpurpose i/o port c bit 10bit 10 of the generalpurpose i/o port c. cd1 carrier detect modem line for scc1. tgate1 timer 1/timer 2 gate signal. pc[9] cts2 l18 bidirectional generalpurpose i/o port c bit 9bit 9 of the generalpurpose i/o port c. cts2 clear to send modem line for scc2. pc[8] cd2 tgate2 m18 bidirectional generalpurpose i/o port c bit 8bit 8 of the generalpurpose i/o port c. cd2 carrier detect modem line for scc2. tgate2 timer 3/timer 4 gate signal. pc[7] cts3 l1tsyncb sdack2 m16 bidirectional generalpurpose i/o port c bit 7bit 7 of the generalpurpose i/o port c. cts3 clear to send modem line for scc3. l1tsyncbtransmit sync input for the serial interface tdm port b. sdack2 sdma acknowledge 2 output that is used as a peripheral interface signal for idma emulation or as a cam interface signal for ethernet. pc[6] cd3 l1rsyncb r19 bidirectional generalpurpose i/o port c bit 6bit 6 of the generalpurpose i/o port c. cd3 carrier detect modem line for scc3. l1rsyncbreceive sync input for the serial interface tdm port b. pc[5] cts4 l1tsynca sdack1 t18 bidirectional generalpurpose i/o port c bit 5bit 5 of the generalpurpose i/o port c. cts4 clear to send modem line for scc4. l1tsyncatransmit sync input for the serial interface tdm port a. sdack1 sdma acknowledge 1output that is used as a peripheral interface signal for idma emulation or as a cam interface signal for ethernet. pc[4] cd4 l1rsynca t17 bidirectional generalpurpose i/o port c bit 4bit 4 of the generalpurpose i/o port c. cd4 carrier detect modem line for scc4. l1rsyncareceive sync input for the serial interface tdm port a. pd[15] l1tsynca u17 bidirectional generalpurpose i/o port d bit 15bit 15 of the generalpurpose i/o port d. l1tsyncainput transmit data sync signal to the tdm channel a. pd[14] l1rsynca v19 bidirectional generalpurpose i/o port d bit 14bit 14 of the generalpurpose i/o port d. l1rsyncainput receive data sync signal to the tdm channel a. 24/96 tspc860 table 10. signal descriptions name description type number reset pd[13] l1tsyncb v18 bidirectional generalpurpose i/o port d bit 13bit 13 of the generalpurpose i/o port d. l1tsyncbinput transmit data sync signal to the tdm channel b. pd[12] l1rsyncb hiz r16 bidirectional generalpurpose i/o port d bit 12bit 12 of the generalpurpose i/o port d. l1rsyncbinput receive data sync signal to the tdm channel b. pd[11] rxd3 t16 bidirectional generalpurpose i/o port d bit 11bit 11 of the generalpurpose i/o port d. rxd3receive data for serial channel 3. pd[10] txd3 w18 bidirectional generalpurpose i/o port d bit 10bit 10 of the generalpurpose i/o port d. txd3transmit data for serial channel 3. pd[9] rxd4 v17 bidirectional generalpurpose i/o port d bit 9bit 9 of the generalpurpose i/o port d. rxd4receive data for serial channel 4. pd[8] txd4 w17 bidirectional generalpurpose i/o port d bit 8bit 8 of the generalpurpose i/o port d. txd4transmit data for serial channel 4. pd[7] rts3 t15 bidirectional generalpurpose i/o port d bit 7bit 7 of the generalpurpose i/o port d. rts3 active low request to send output indicates that scc3 is ready to transmit data. pd[6] rts4 v16 bidirectional generalpurpose i/o port d bit 6bit 6 of the generalpurpose i/o port d. rts4 active low request to send output indicates that scc4 is ready to transmit data. pd[5] reject2 u15 bidirectional generalpurpose i/o port d bit 5bit 5 of the generalpurpose i/o port d. reject2 this input to scc2 allows a cam to reject the current ethernet frame after it determines the frame address did not match. pd[4] reject3 u16 bidirectional generalpurpose i/o port d bit 4bit 4 of the generalpurpose i/o port d. reject3 this input to scc3 allows a cam to reject the current ethernet frame after it determines the frame address did not match. pd[3] reject4 w16 bidirectional generalpurpose i/o port d bit 3bit 3 of the generalpurpose i/o port d. reject4 this input to scc4 allows a cam to reject the current ethernet frame after it determines the frame address did not match. tspc860 25/96 table 10. signal descriptions name description type number reset tck dsck hiz(pulled up on rev 0 to rev a.3) h16 input provides clock to scan chain logic or for the development port logic. should be tied to vcc if jtag or development port are not used. tms pulled up g18 input controls the scan chain test mode operations. should be tied to power (1) through a pullup resistor if unused. tdi dsdi pulled up (hiz on rev 0 to rev a.3) h17 input input serial data for either the scan chain logic or the development port and determines the operating mode of the development port at reset. tdo dsdo low g17 output output serial data for either the scan chain logic or for the development port. trst pulled up g19 input reset for the scan chain logic. if jtag is not used, connect trst to ground. if jtag is used, connect trst to poreset . in case poreset logic is powered by the keepalive power supply (kapwr), connect trst to poreset through a diode (anode connected to trst and cathode to poreset ). spare[14] hiz b7, h18, v15, h4 noconnect spare signalsnot used on current chip revisions. leave unconnected. power supply see figure 4 power vddlpower supply of the internal logic. vddhpower supply of the i/o buffers and certain parts of the clock control. vddsynpower supply of the pll circuitry. kapwrpower supply of the internal oscm, rtc, pit, dec, and tb. vssground for circuits, except for the pll circuitry. vsssyn, vsssyn1ground for the pll circuitry. 3.2. active pull-up buffers active pull-up buffers are a special variety of bidirectional three-state buffer with the following properties: when enabled as an output and driving low, they behave as a normal output driver (that is, the pin is constantly driven low). when enabled as an output and driving high, drive high until an internal detection circuit determines that the output has reach ed the logic high threshold and then stop driving (that is, the pin switches to high-impedance). when disabled as an output or functioning as an input, it should not be driven. due to the behavior of the buffer when being driven high, a pull-up resistor is required externally to function as a `bus keep' for these shared signals in periods when no drivers are active and to keep the buffer from oscillating when the buffer is driving high, b ecause if the voltage ever dips below the logic high threshold while the buffer is enabled as an output, the buffer will reactivate. furt her, external logic must not attempt to drive these signals low while active pull-up buffers are enabled as outputs, because the buffers will reactivate and drive high, resulting in a buffer fight and possible damage to the tspc860, to the system, or to both. figure 6 compares three-state buffers and active pull-up buffers graphically in general terms. it makes no implication as to wh ich edges trigger which events for any particular signal. 26/96 tspc860 threestate buffer 1 2 3 1 drive high on one edge 2 switch to hiz on later edge 3 pullup resistor maintains logic high state 12 3 1 drive high on one edge 2 switch to hiz when active pullup buffer 5 4 threshold voltage (voh+margin) is reached 3 pullup resistor maintains logic high state 4 disable buffer as output 5 pullup resistor maintains logic high state; other driver can drive signal note: events 1 and 4 can be in quick succession. figure 6 : three-state buffers and active pull-up buffers table 11 summarizes when active pull-up drivers are enabled as outputs. table 11. active pull-up resistors enabled as outputs signal description ts , bb when the tspc860 is the external bus master throughout the entire bus cycle. bi when the tspc860's memory controller responds to the access on the external bus, throughout the entire bus cycle. ta when the tspc860's memory controller responds to the access on the external bus, then: ? for chip-selects controlled by the gpcm set for external ta , the tspc860's ta buffer is not enabled as an output. ? for chip-selects controlled by the gpcm set to terminate in n wait-states, ta is enabled as an output on cycle (n-1) and driven high, then is driven low on cycle n, terminating the bus transaction. external logic can drive ta at any point before this, thus terminating the cycle early. [for example, assume the gpcm is programmed to drive ta after 15 cycles. if external logic drives ta before 14 clocks have elapsed then the ta will be accepted by the tspc860 as a cycle termination.] ? for chip-selects controlled by the upm, the ta buffer is enabled as an output throughout the entire bus cycle. the purpose of active pull-up buffers is to allow access to zero wait-state logic that drives a shared signal on the clock cycl e immedi- ately following a cycle in which the signal is driven by the tspc860. in other words, it eliminates the need for a bus turn-aro und cycle. 3.3. internal pull-up and pull-down resistors the tms and trst pins have internal pull-up resistors. tspc860 devices from rev 0 to rev a.3 (masks xe64c and xf84c) have an internal pull-up resistor on tck/dsck but no internal pull-up resistor on tdi/dsdi. this was corrected on rev b and later; on t hese chips, the internal pull-up resistor was removed from tck/dsck and an internal pull-up resistor was added to tdi/dsdi. if rstconf is pulled down, during hardware reset (initiated by hreset or poreset ), the data bus d[031] is pulled down with internal pull-down resistors. these internal pull-down resistors are to provide a logic-zero default for these pins when progra mming the hard reset configuration word. these internal pull-down resistors are disconnected after hreset is negated. no other pins have internal pull-ups or pull-downs. tspc860 27/96 resistance values for internal pull-up and pull-down resistors are not specified because their values may vary due to process v aria- tions and shrinks in die size, and they are not tested. typical values are on the order of 5 k but can vary by approximately a factor of 2. 3.4. recommended basic pin connections 3.4.1.reset configuration some external pin configuration is determined at reset by the hard reset configuration word. thus, some decisions as to system con- figuration (for example, location of bdm pins) should be made before required application of pull-up and pull-down resistors ca n be determined. rstconf should be grounded if the hard reset configuration word is used to configure the tspc860 or should be connected to vcc if the default configuration is used. pull-up resistors may not be used on d[031] to set the hard reset configuration word, as the values of the internal pull-down resistors are not specified or guaranteed. to change a data bus signal from its default logic low state during reset, actively drive that signal high. modck[12] must be used to determine the default clocking mode for the tspc860. after hardware reset, the modck[12] pins change function and become outputs. thus, if these alternate functions are also desired, then the modck[12] configuration shou ld be set with three-state drivers that turn off after hreset is negated; however, if modck[12] pins' alternate output functions are not used in the system, they can be configured with pull-up and pull-down resistors. 3.3.1.1.reset configuration signals with open-drain buffers and active pull-up buffers (hreset , sreset , tea , ts , ta , bi , and bb ) must have external pull-up resistors. these signals include the following: some other input signals do not absolutely require a pull-up resistor, as they may be actively driven by external logic. howeve r, if they are not used externally, or if the external logic connected to them is not always actively driving, they may need external pull -up resis- tors to hold them negated. these signals include the following: poreset as cr/irq3 kr/retry /irq4 /spkrout (if configured as kr /retry or irq4 ) any irqx (if configured as irqx ) br (if the tspc860's internal bus arbiter is used) bg (if an external bus arbiter is used) 3.4.2. jtag and debug ports tck/dsck or ale_b/dsck/at1 (depending on the configuration of the dsck function) should be connected to ground through a pull-down resistor to disable debug mode as a default. when required, a debug mode controller tool externally drives this signa l high actively to put the tspc860 into debug mode. two pins need special attention, depending on the version of tspc860 used. for tspc860 rev b and later, tdi/dsdi should be pulled up to vcc to keep it from oscillating when unused. for tspc860 rev a.3 and earlier, tck/dsck should be connected to ground if it is configured for its dsck function, as stated above. however, for these versions of the tspc860, the pull-down resistor must be strong (for example, 1 k to overcome the internal pull-up resistor. to allow application of any version of processor, perform both of the above actions. 3.4.3.unused inputs in general, pull-up resistors should be used on any unused inputs to keep them from oscillating. for example, if pcmcia is not used, the pcmcia input pins (wait_a, wait_b, ip_a[08], ip_b[08]) should have external pull-up resistors. however, unused pins of port a, b, c, or d can be configured as outputs, and, if they are configured as outputs they do not require external terminatio ns. 3.4.4.unused outputs unused outputs can be left unterminated. 3.5. signal states during hardware reset during hardware reset (hreset or poreset ), the signals of the tspc860 behave as follows: the bus signals are high-impedance. the port i/o signals are configured as inputs, and are therefore high-impedance. the memory controller signals are driven to their inactive state. however, some signal functions are determined by the reset configuration. when hreset is asserted, these signals immediately begin functioning as determined by the reset configuration and are either high-impedance or are drive to their inactive state a ccord- ingly. the behavior of these signals is shown in table 12. 28/96 tspc860 table 12. signal states during hardware reset signal behavior bdip /gpl_b5 bdip : high impedance gpl_b5 : high rsv /irq2 rsv : high irq2 : high impedance kr /retry /irq4 /spkrout kr /retry /irq4 : high impedance spkrout: low frz/irq6 frz: low irq6 : high impedance ale_b/dsck/at1 ale_b: low dsck/at1: high impedance ip_b[01]/iwp[01]/vfls[01] ip_b[01]: high impedance. iwp[01]: high vfls[01]: low ip_b3/iwp2/vf2 ip_b3: high impedance iwp2: high vf2: low ip_b4/lwp0/vf0 ip_b4: high impedance lwp0: high vf0: low ip_b5/lwp1/vf1 ip_b5: high impedance lwp1: high; vf1: low tspc860 29/96 b. detailed specifications 1. scope this drawing describes the specific requirements for the microcontroller tspc860, in compliance atmel-grenoble standard scree- ning. 2. applicable documents quality levels for supplied components sq32s0100.0. 3. requirements 3.1. general the microcircuits are in accordance with the applicable documents and as specified herein. 3.2. design and construction 3.2.1.terminal connections the terminal connections shall be as shown in chap a. general description. 3.2.2.lead material and finish lead material and finish shall be as specified at 11. 3.2.3.package the macrocircuits are packaged in 357 ceramic ball grid array packages. the precise case outlines are described at the end of the specification ( 11.1). 3.3. absolute maximum ratings stresses above the absolute maximum rating may cause permanent damage to the device. extended operation at the maximum levels may degrade performance and affect reliability. table 1 : absolute maximum rating for the tspc860 parameter symbol min max unit i/o supply voltage v ddh -0.3 4.0 v internal supply voltage v ddl -0.3 4.0 v backup supply voltage kapwr -0.3 4.0 v pll supply voltage v ddsyn -0.3 4.0 v input voltage v in -0.3 5.8 v storage temperature range t stg -55 +150 c 30/96 tspc860 3.4. thermal characteristics table 2 : thermal characteristics characteristic symbol value unit thermal resistance for bga (1) (junction-to-ambient) q ja 47 (2) c/w q ja 30 (3) c/w q ja 15 (4) c/w thermal resistance for bga (junction-to-case) (top) q jc 4.9 c/w note : (1) for more information on the design of thermal vias on multilayer boards and bga layout considerations in general, refer to motorola's documentation an-1231/d, plastic ball grid array application note. (2) assumes natural convection and a single layer board (no thermal vias). (3) assumes natural convection, a multilayer board with thermal vias, 1w pc860 dissipation, and a board temperature rise of 20 c above ambient. (4) assumes natural convection, a multilayer board with termal vias, 1w pc860 dissipation, and a board temperature rise of 10 c above ambient. table 3 : power dissipation (p d ) die revision frequency typical 1 maximum 2 unit b and later 33 mhz 375 460 mw 50 mhz 575 700 mw 66 mhz 750 900 mw note : 1 typical power dissipation is measured at 3.3 v. 2 maximum power dissipation is measured at 3.65 v. 3.5. marking the document where are defined the marking are identified in the related reference documents. each microcircuit are legible and permanently marked with the following information as minimum : - thomson logo, - manufacturer's part number, - date-code of inspection lot, - esd identifier if available, - country of manufacturing. 4. electrical characteristics 4.1. general requirements all static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below. tspc860 31/96 4.2. dc electrical specifications table 4 : dc electrical specification vcc = 3.3 5 % v dc, gnd = 0 v dc, -55 c t c 125 c characteristic symbol min max unit operating voltage vddh, vddl, kapwr, vddsyn 3.135 3.465 v kapwr (power-down mode) 2.0 3.6 v kapwr (all other opera- ting modes) vddh - 0.4 vddh v input high voltage (all inputs except extal and extclk) vih 2.0 5.5 v input low voltage vil gnd 0.8 v extal, extclk input high voltage vihc 0.7*(vcc) vcc+0.3 v input leakage current, vin = 5.5v (except tms, trst, dsck and dsdi pins) i in - 100 a input leakage current, vin = 3.6v (except tms, trst, dsck and dsdi pins) i in - 10 a input leakage current, vin = 0v (except tms, trst, dsck and dsdi pins) i in - 10 a output high voltage, ioh = -2.0 ma, vddh = 3.0v except xtal, xfc, and open drain pins voh 2.4 - v 32/96 tspc860 output low voltage iol = 2.0 ma clkout iol = 3.2 ma a(0:31), tsiz0/reg, tsiz1, d(0:31), dp(0:3)/irq (3:6), rd/wr , burst , rsv/irq2 , ip_b(0:1)/iwp(0:1)/vfls(0:1), ip_b2/iois16_b/at2, ip_b3/iwp2/vf2, ip_b4/lwp0/vf0, ip_b5/lwp1/vf1, ip_b6/dsdi/at0, ip_b7/ptr/ at3, rxd1 /pa15, rxd2/pa13 , l1txdb/pa11, l1rxdb/pa10, l1txda/pa9, l1rxda/pa8, tin1/l1rclka/brgo1/clk1/pa7, brgclk1/tout1 /clk2/pa6, tin2/l1tclka/ brgo2/clk3/pa5, tout2 /clk4/pa4, tin3/brgo3/clk5/pa3, brgclk2/l1rclkb/tou- t3 /clk6/pa2, tin4/brgo4/clk7/pa1, l1tclkb/ tout4 /clk8/pa0, rrjct1/spisel/pb31, spiclk/pb30, spimosi/pb29, brgo4/spimiso/ pb28, brgo1/i2csda/pb27, brgo2/i2cscl/ pb26, smtxd1/pb25, smrxd1/pb24, smsyn1/sdack1/pb23, smsyn2/sdack2/pb22, smtxd2/l1clkob/pb21, smrxd2/l1clkoa/ pb20, l1st1/rts1/pb19, l1st2/rts2/pb18, l1st3/l1rqb/pb17, l1st4/l1rqa/pb16, brgo3/pb15, rstrt1 /pb14, l1st1/rts1/dreq0/pc15, l1st2/rts2/dreq1/pc14, l1st3/l1rqb/pc13, l1st4/l1rqa/pc12, cts1/pc11, tgate1/cd1/pc10, cts2/pc9, tgate2/cd2/pc8, cts 3 / sdack2/l1tsyncb/pc7, cd3 / l1rsyncb/pc6, cts4 / sdack1/l1tsynca/pc5, cd4 / l1rsynca/pc4, pd15/l1tsynca , pd14/l1rsynca , pd13/l1tsyncb , pd12/l1rsyncb , pd11/rxd3 , pd10/txd3 , pd9/rxd4 , pd8/txd4 , pd5/rrjct2 , pd6/rts4 , pd7/rts3 , pd4/rrjct3 , pd3 iol = 5.3 ma bdip /gpl_b(5), br , bg , frz/irq6, cs (0:5), cs (6)/ce (1)_b, cs (7)/ce (2)_b, we0 /bs _b0/iord , we1 /bs _b1/iowr , we2 /bs _b2/pcoe , we3 /bs _b3/pcwe , bs _a(0:3), gpl_a0/gpl_b0, oe /gpl_a1/gpl_b1, gpl_a(2:3)/gpl_b(2:3)/cs (2:3), upwaita/gpl_a4, upwaitb/gpl_b4, gpl_a5, ale_a, ce 1_a, ce 2_a, ale_b/dsck/at1, op(0:1), op2/modck1/sts , op3/modck2/dsdo, baddr(28:30) iol = 7.0 ma txd1/pa14, txd2/pa12 iol = 8.9 ma ts , ta , tea , bi , bb , hreset , sreset vol - 0.5 v input capacitance cin - 20 pf tspc860 33/96 4.3. ac electrical specifications control timing figure 7 : ac electrical specifications control timing diagram clkout outputs inputs inputs 2.0v 0.8v 2.0v 2.0v 0.8v 0.8v 2.0v 2.0v 0.8v 0.8v 2.0v 2.0v 0.8v 0.8v 2.0v a b cd cd a.maximum output delay specification b.minimum output hold time c.minimum input setup time specification d.minimum input hold time specification outputs 2.0v 0.8v 0.8v 2.0v a b 0.8v the timing for the tspc860 bus shown assumes a 50-pf load for maximum delays and a 0-pf load for minimum delays. for loads other than 50 pf, maximum delays can be derated by 1 ns per 10 pf when operating at frequencies other than the frequency marked on the part, new bus timing must be calculated for all frequency- de- pendent ac parameters. frequency-dependent ac parameters are those with an entry in the 'ffact'. column. ac parameters with- out an ffactor entry are not frequency-dependent and therefore do not need to be recalculated. 34/96 tspc860 to calculate the ac parameters for a frequency f, the following equation should be applied to each one of the above parameters : for minima : d = d 50 + ffactor (1000 - 20 x f) f where d is the parameter value in nanoseconds for the frequency required f is the operation frequency in mhz d50 is the parameter defined for 50 mhz ffactor is the one defined for each on of the parameters in the table. vcc = 3.3 5 % v dc, gnd = 0 v dc, -55 c t c 125 c table 5 : bus operation timings characteristic 50mhz 33mhz 1 unit ffactor min max min max b1 clkout period 20 30.30 ns b1a extclk to clkout phase skew (extclk>15mhz and mf <=2) -0.90 0.90 -0.90 0.90 ns b1b extclk to clkout phase skew (extclk>10mhz and mf <10) -2.30 2.30 -2.30 2.30 ns b1c clkout phase jitter (extclk>15mhz and mf <=2) -0.60 0.60 -0.60 0.60 ns b1d clkout phase jitter 2 -2.00 2.00 -2.00 2.00 ns b1e clkout frequency jitter (mf<10) 2 0.50 0.50 % b1f clkout frequency jitter (10 tspc860 35/96 characteristic 50mhz 33mhz 1 unit ffactor min max min max b8 clkout to a(0:31), baddr(28:30), rd/wr , burst , d(0:31), dp(0:3) valid 5.00 11.75 7.58 14.33 ns 0.250 b8a 1c clkout to tsiz(0:1),reg , rsv , at(0:3), bdip , ptr valid 5.00 11.75 7.58 14.33 ns 0.250 b8b 1d clkout to br , bg , vfls(0:1), vf(0:2), iwp(0:2), frz, lwp(0:1), sts valid 4 5.00 11.75 7.58 14.33 ns 0.250 b9 clkout to a(0:31), baddr(28:30), rd/wr , burst , d(0:31), dp(0:3), tsiz(0:1),reg , rsv , at(0:3), ptr high z 5.00 11.75 7.58 14.33 ns 0.250 b10 ns b11 clkout to ts , bb assertion 5.00 11.00 7.58 13.58 ns 0.250 b11a 1e clkout to ta , bi assertion (when driven by the memory controller or pcmcia i/f) 2.50 9.25 2.5 9.25 ns - b12 clkout to ts , bb negation 5.00 11.75 7.58 14.33 ns 0.250 b12a 1f clkout to ta , bi negation (when driven by the memory controller or pcmcia interface) 2.50 11.00 2.50 11.00 ns - b13 clkout to ts , bb high z 5.00 19.00 7.58 21.58 ns 0.25 b13a 1g clkout to ta , bi high z (when driven by the memory controller or pcmcia interface) 2.50 15.00 2.50 15.00 ns - b14 clkout to tea assertion 2.50 10.00 2.50 10.00 ns - b15 clkout to tea high z 2.50 15.00 2.50 15.00 ns - b16 ta , , bi valid to clkout (setup time) 9.75 9.75 ns b16a 1h tea , kr , retry , cr valid to clkout (setup time) 10.00 10.00 ns b16b bb, bg, br, valid to clkout (setup time) 5 8.50 8.50 ns b17 clkout to ta , tea , bi , bb , bg , br valid (hold time) 1.00 1.00 ns b17a 1i clkout to kr , retry , cr valid (hold time) 2.00 2.00 ns b18 d(0:31), dp(0:3) valid to clkout rising edge (setup time) 6 6.00 6.00 ns b19 clkout rising edge to d(0:31), dp(0:3) valid (hold time) 6 1.00 1.00 ns b20 d(0:31), dp(0:3) valid to clkout falling edge (setup time) 7 4.00 4.00 ns 36/96 tspc860 characteristic 50mhz 33mhz 1 unit ffactor min max min max b21 clkout falling edge to d(0:31), dp(0:3) valid (hold time) 7 2.00 2.00 ns b22 clkout rising edge to cs asserted -gpcm- acs = 00 5.00 11.75 7.58 14.33 ns 0.250 b22a 1j clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0, ebdf =0 8.00 8.00 ns b22b 1k clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0, ebdf = 0 5 11.75 7.58 14.33 ns 0.250 b22c 1l clkout falling edge to cs asserted -gpcm- acs = 11, trlx = 0, ebdf = 1 7.00 14.13 10.86 17.99 ns 0.375 b23 clkout rising edge to cs negated gpcm read access, 1m gpcm write access, acs = `00', trlx = `0' & csnt = `0' 2.00 8.00 2.00 8.00 ns b24 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 0 3.00 5.58 ns 0.250 b24a 1n a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11, trlx = 0 8.00 13.15 ns 0.500 b25 clkout rising edge to oe , we (0:3) asserted 9.00 9.00 ns b26 clkout rising edge to oe negated 2.00 9.00 2.00 9.00 ns b27 a(0:31) and baddr(28:30) to cs asserted gpcm acs = 10, trlx = 1 23.00 35.88 ns 1.250 b27a a(0:31) and baddr(28:30) to cs asserted gpcm acs = 11, trlx = 1 28.00 43.45 ns 1.500 b28 clkout rising edge to we(0:3) negated gpcm write access csnt = 0 9.00 9.00 ns b28a clkout falling edge to we (0:3) negated gpcmwite access trlx = 0, csnt = 1, ebdf = 0 5.00 11.75 7.58 14.33 ns 0.250 b28b 1o clkout falling edge to we (0:3) negated gpcmwrite access trlx = `0', csnt = `1', ebdf=0 11.75 14.33 ns 0.250 b28c 1p clkout falling edge to we (0:3) negated gpcmwrite access trlx = `0', csnt = `1' write access trlx = 0, csnt = 1, ebdf = 1 7.00 14.13 10.86 17.99 ns 0.375 b28d 1q clkout falling edge to cs negated negated gpcmwrite access trlx = `0', csnt = `1, acs =10, or acs = 11', ebdf=1 14.13 17.99 ns 0.375 tspc860 37/96 characteristic 50mhz 33mhz 1 unit ffactor min max min max b29 1r we (0:3) negated to dp (0:3) highzgpcmwrite access, csnt = 0, ebdf = 0 3.00 5.58 ns 0.250 b29a 1s we (0:3) negated to d(0:31), dp(0:3) high z gpcm write access, trlx = `0', csnt = 1', ebdf = 0 8.00 13.15 ns 0.500 b29b 1t cs negated to d(0:31), dp(0:3) high z gpcm write access, acs = `00', trlx = `0' & csnt = `0' 3.00 5.58 ns 0.250 b29c 1u cs negated to d(0:31), dp(0:3) high z gpcm write access, trlx = `0', csnt = `1 ', acs = `11,', ebdf = 0 8.00 13.15 ns 0.500 b29d 1v we (0:3) negated to d(0:31), dp(0:3) high z gpcm write access, trlx = `1', csnt = ` 1', ebdf = 0 28.00 43.45 ns 1.500 b29e cs negated to d (0:31), dp(0:3) high z gpcm write access, trlx = 1, csnt = 1, acs =10, or acs =11 ebdf = 0 28.00 43.45 ns 1.500 b29f 1w we (0:3) negated to d(0:31), dp(0:3) high z gpcm write access, trlx = `0', csnt = ` 1', ebdf = 1 5.00 8.86 ns 0.375 b29g 1x cs negated to d(0:31), dp(0:3) high z gpcm write access, trlx = `0', csnt = `1', acs = `10' or acs='11' , ebdf = 1 5.00 8.86 ns 0.375 b29h 1y we (0:3) negated to d(0:31), dp(0:3) high z gpcm write access, trlx = `1', csnt = ` 1', ebdf = 1 24.50 38.67 ns 1.375 b29i 1z cs negated to d(0:31), dp(0:3) high z gpcm write access, trlx = `1', csnt = `1', acs = `10' or acs='11 ', ebdf =1 24.50 38.67 ns 1.375 b30 cs , we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access 8 3.00 5.58 0.250 b30a 1aa we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access, trlx='0', csnt = '1'. cs negated to a(0:31) invalid gpcm write access, trlx='0', csnt = '1', acs = 10 ,acs = ='1 1' , ebdf = 0 8.00 13.15 ns 0.500 38/96 tspc860 characteristic 50mhz 33mhz 1 unit ffactor min max min max b30b 1ab we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access, trlx='1', csnt = '1'. 1ac cs negated to a(0:31) invalid gpcm write access, trlx='1', csnt = '1', acs = 10 ,acs = ='1 1' , ebdf = 0 28.00 43.45 ns 1.500 b30c 1ad we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access, trlx='0', csnt = '1'. cs negated to a(0:31) invalid gpcm write access, trlx='0', csnt = '1', acs = 10 ,acs = ='11 ', ebdf = 1 4.50 8.36 ns 0.375 b30d 1ae we (0:3) negated to a(0:31), baddr(28:30) invalid gpcm write access, trlx='1', csnt = '1'. 1af cs negated to a(0:31) invalid gpcm write access, trlx='1', csnt = '1', acs = 10 ,acs = ='11 ' , ebdf = 1 24.50 38.67 ns 1.375 b31 clkout falling edge to cs valid as requested by control bit cst4 in the corresponding word in the upm 1.5 6.00 1.50 6.00 ns b31a 1ag clkout falling edge to cs valid as requested by control bit cst1 in the corresponding word in the upm 5.00 11.75 7.58 14.33 ns 0.250 b31b 1ah clkout rising edge to cs valid as requested by control bit cst2 in the corresponding word in the upm 1.50 8.00 1.50 8.00 ns b31c 1ai clkout rising edge to cs valid as requested by control bit cst3 in the corresponding word in the upm 5.00 11.75 7.58 14.33 ns 0.250 b31d 1aj clkout falling edge to cs valid as requested by control bit cst1 in the corresponding word in the upm, ebdf = 1 9.40 14.13 13.26 17.99 ns 0.375 b32 clkout falling edge to bs valid as requested by control bit bst4 in the corresponding word in the upm 1.50 6.00 1.50 6.00 ns b32a 1ak clkout falling edge to bs valid as requested by control bit bst1 in the corresponding word in the upm, ebdf = 0 5 11.75 7.58 14.33 ns 0.250 b32b 1al clkout rising edge to bs valid as requested by control bit bst2 in the corresponding word in the upm 1.50 8.00 1.50 8.00 ns b32c 1am clkout rising edge to bs valid as requested by control bit bst3 in the corresponding word in the upm 5.00 11.75 7.58 14.33 ns 0.25 tspc860 39/96 characteristic 50mhz 33mhz (1) unit ffactor min max min max b32d 1an clkout falling edge to bs valid as requested by control bit bst1 in the corresponding word in the upm, ebdf = 1 9.40 14.13 13.26 17.99 ns 0.375 b33 clkout falling edge to gpl valid as requested by control bit gxt4 in the corresponding word in the upm 1.50 6.00 1.50 6.00 ns b33a 1ao clkout rising edge to gpl valid as requested by control bit gxt3 in the corresponding word in the upm 5.00 11.75 7.58 14.33 ns 0.250 b34 a(0:31), baddr(28:30), and d(0:31) to cs valid as requested by control bit cst4 in the corresponding word in the upm 3 5.58 ns 0.250 b34a 1ap a(0:31), baddr(28:30), and d(0:31) to cs valid as requested by control bit cst1 in the corresponding word in the upm 8.00 13.15 ns 0.500 b34b 1aq a(0:31), baddr(28:30), and d(0:31) to cs valid as requested by control bit cst2 in the corresponding word in the upm 13 20.73 ns 0.750 b35 a(0:31), baddr(28:30), and d(0:31) to bs valid as requested by control bit bst4 in the corresponding word in the upm 3.00 5.58 ns 0.250 b35a 1ar a(0:31), baddr(28:30), and d(0:31) to bs valid as requested by control bit bst1 in the corresponding word in the upm 8.00 13.15 ns 0.500 b35b 1as a(0:31), baddr(28:30), and d(0:31) to bs valid as requested by control bit bst2 in the corresponding word in the upm 13.00 20.73 ns 0.750 b36 a(0:31), baddr(28:30), and d(0:31) to gpl valid as requested by control bit gxt4 in the corresponding word in the upm 3.00 5.58 ns 0.250 b37 upwait valid to clkout faling edge 9 6.00 6.00 ns b38 clkout falling edge to upwait valid 9 1.00 1.00 ns b39 as valid to clkout rising edge 10 7.00 7.00 ns b40 a(0:31), tsiz(0:1), rd/wr , burst , valid to clkout rising edge. 7.00 7.00 ns b41 ts valid to clkout rising edge (setup time). 7.00 7.00 ns b42 clkout rising edge to ts valid (hold time). 2.00 2.00 ns b43 as negation to memory controller signals negation tbd ns 40/96 tspc860 1. the values in the 33 mhz column are derived from the 50 mhz values. 2. phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value. 3. if the rate of change of the frequency of extal is slow (i.e. it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e. it does not stay at an extreme value for a long time) then the maxim um allowed jitter on extal can be up to 2 %. 4. the timing for br output is relevant when the pc860 is selected to work with external bus arbiter. the timing for bg output is relevant when the pc860 is selected to work with internal bus arbiter. 5. the timing required for br input is relevant when the mpc860 is selected to work with internal bus arbiter. the timing for bg input is relevant when the pc860 is selected to work with external bus arbiter. 6. the d (0:31) and dp (0:3) input timings b20 and b21 refer to the rising edge of the clkout in which the ta input signal is asserted. 7. the d (0:31) and dp (0:3) input timings b20 and b21 refer to the falling edge of the clkout. this timing is valid only for read accesses controlled by chip-selects under control of the upm in the memory controller, for data beats where dlt3 = 1 in the upm ram words. (this is only the cases where data is latched on the falling edge of clkout). 8. the timing b30 refers to cs when acs = 00 and to we (0:3) when csnt = 0 9. the signal upwait is considered asynchronous to the clkout and synchronized internally. the timings specified in b37 and b38 are specified to enable the freeze of the upm output signals as described in figure 22. 10. the as signal is considered asynchronous to the clkout. the timing b39 is specified in order to allow the behavior specified in figure 25. tspc860 41/96 figure 8 : external clock timing figure 9 : synchronous output signals timing 42/96 tspc860 figure 10 : synchronous active pullup and open drain outputs signals timing figure 11 : synchronous input signals timing tspc860 43/96 figure 12 : input data timing in normal case figure 13 : input data timing when controlled by upm in the memory controller 44/96 tspc860 figure 14 : external bus read timing (gpcm controlled - acs = `00') figure 15 : external bus read timing (gpcm controlled - trlx = `0' acs = `10') tspc860 45/96 figure 16 : external bus read timing (gpcm controlled - trlx = `0' acs = `11') figure 17 : external bus read timing (gpcm controlled -trlx = `1', acs = `10', acs = `11') 46/96 tspc860 figure 18 : external bus write timing (gpcm controlled - trlx = `0', csnt = `0') tspc860 47/96 figure 19 : external bus write timing (gpcm controlled - trlx = `0', csnt = `1') 48/96 tspc860 figure 20 : external bus write timing (gpcm controlled - trlx = `1', csnt = `1') tspc860 49/96 figure 21 : external bus timing (upm controlled signals) 50/96 tspc860 figure 22 : asynchronous upwait asserted detection in upm handled cycles timing tspc860 51/96 figure 23 : asynchronous upwait negated detection in upm handled cycles timing figure 24 : synchronous external master access timing - gpcm handled acs = `00' 52/96 tspc860 figure 25 : asynchronous external master memory access timing (gpcm controlled-acs = '00') figure 26 : asynchronous external master - control signals negation time table 6 : interrupt timing num characteristic 33mhz 50mhz unit min max min max i39 irq x valid to clkout rising edge (set up time) 6.00 6.00 ns i40 irq x hold time after clkout 2.00 2.00 ns i41 irq x pulse width low 3.00 3.00 ns i42 irq x pulse width high 3.00 3.00 ns i43 irq x edge to edge time 4xt- clockout 4xt clockout - notes: the timings i39 and i40 describe the testing conditions under which the irq lines are tested when beeing defined as level sensitive. the irq lines are synchronized internally and do not have to be asserted or negated with reference to the clkout. the timings i41, i42 and i43 are specified to allow the correct function of the irq lines detection circuitry, and has no direct relation with the total system interrupt latency that the tspc860 is able to support. tspc860 53/96 figure 27 : interrupt detection timing for external level sensitive lines figure 28 : interrupt detection timing for external edge sensitive lines table 7 : pcmcia timing characteristic 33mhz 50mhz ffactor unit min max min max p44 a(0:31), reg valid to pcmcia strobe asserted. 1 20.73 13.00 0.750 ns p45 a(0:31), reg valid to ale negation. 1 28.30 18.00 1.000 ns p46 clkout to reg valid 7.58 15.58 5.00 13.00 0.250 ns p47 clkout to reg invalid. 8.58 6.00 0.250 ns p48 clkout to ce 1, ce 2 asserted. 7.58 15.58 5.00 13.00 0.250 p49 clkout to ce 1, ce 2 negated. 7.58 15.58 5.00 13.00 0.250 ns p50 clkout to pcoe , iord , pcwe , iowr assert time. 11.00 11.00 - ns p51 clkout to pcoe , iord , pcwe , iowr negate time. 2.00 11.00 2.00 11.00 - ns p52 clkout to ale assert time 7.58 15.58 5.00 13.00 0.250 ns p53 clkout to ale negate time 15.58 13.00 0.250 ns 54/96 tspc860 p54 pcwe , iowr negated to d(0:31) invalid 1 5.58 3.00 0.250 ns p55 waita and waitb valid to clkout rising edge 1 8.00 8.00 ns p56 clkout rising edge to waita and waitb invalid. 1 2.00 2.00 ns notes: psst = 1. otherwise add psst times cycle time. psht = 1. otherwise add psht times cycle time. these synchronous timings define when the waitx signals are detected in order to freeze (or relieve) the pcmcia current cycle. the waitx assertion will be effective only if it is detected 2 cycles before the psl timer expiration. figure 29 : pcmcia access cycles timing external bus read tspc860 55/96 figure 30 : pcmcia access cycles timing external bus write figure 31 : pcmcia wait signals detection timing 56/96 tspc860 table 8 : pcmcia port timing characteristic 33mhz 50mhz ffactor unit min max min max p57 clkout to opx valid 19.00 19.00 ns p58 hreset negated to opx drive 1 25.73 18.00 0.75 ns p59 ip_xx valid to clkout rising edge 5.00 5.00 ns p60 clkout rising edge to ip_xx invalid 1.00 1.00 ns note: op2 and op3 only. figure 32 : pcmcia output port timing tspc860 57/96 figure 33 : pcmcia input port timing table 9 : debug port timing characteristic 33mhz 50mhz unit min max min max d61 dsck cycle time 3xt clockout e 3xt clockout e ns d62 dsck clock pulse width 1.25xt clockout e 1.25xt clockout e ns d63 dsck rise and fall times 0.00 3.00 0.00 3.00 ns d64 dsdi input data setup time 8.00 e 8.00 e ns d65 dsdi data hold time 5.00 e 5.00 e ns d66 dsck low to dsdo data valid 0.00 15.00 0.00 15.00 ns d67 dsck low to dsdo invalid 0.00 2.00 0.00 2.00 ns figure 34 : debug port clock input timing 58/96 tspc860 figure 35 : debug port timings table 10 : reset timing characteristic 33mhz 50mhz ffactor unit min max min max r69 clkout to hreset high impedance 20.00 20.00 ns r70 clkout to sreset high impedance 20.00 20.00 ns r71 rstconf pulse width 515.15 340.00 17.000 ns r72 r73 configuration data to hreset rising edge set up time 504.55 350.00 15.000 ns r74 configuration data to rstconf rising edge set up time 350.00 350.00 ns r75 configuration data hold time after rstconf negation 0.00 0.00 ns r76 configuration data hold time after hreset negation 0.00 0.00 ns r77 hreset and rstconf asserted to data out drive 25.00 25.00 ns r78 rstconf negated to data out high impedance. 25.00 25.00 ns r79 clkout of last rising edge before chip tristates hreset to data out high impedance. 25.00 25.00 ns r80 dsdi, dsck set up 90.91 60.00 3.000 ns r81 dsdi, dsck hold time 0.00 0.00 ns r82 sreset negated to clkout rising edge for dsdi and dsck sample 242.42 160.00 8.000 ns tspc860 59/96 figure 36 : reset timing - configuration from data bus figure 37 : reset timing - tspc860 data bus weak drive during configuration 60/96 tspc860 figure 38 : reset timing - debug port configuration 4.4. ieee 1149.1 electrical specifications table 11 : jtag timing characteristic 33mhz 50mhz unit min max min max j82 tck cycle time 100 100 ns j83 tck clock pulse width measured at 1.5 v 40 40 ns j84 tck rise and fall times 0 10 0 10 ns j85 tms, tdi data setup time 5 5 ns j86 tms, tdi data hold time 25 25 ns j87 tck low to tdo data valid 27 27 ns j88 tck low to tdo data invalid 0 0 ns j90 trst assert time 100 100 ns j91 trst setup time to tck low 40 40 ns j92 tck falling edge to output valid 50 50 ns j93 tck falling edge to ouput valid out of high impedance 50 50 ns j94 tck falling edge to output high impedance 50 50 ns j95 boundary scan input valid to tck rising edge 50 50 ns j96 tck rising edge to boundary scan input invalid 50 50 ns tspc860 61/96 figure 39 : jtag test clock input timing figure 40 : jtag-test access port timing diagram figure 41 : jtag-trst timing diagram 62/96 tspc860 figure 42 : boundary scan (jtag) timing diagram tspc860 63/96 5. cpm electrical characteristics 5.1. pip/pio ac electrical specifications table 12 : pip/pio timing num characteristic all frequencies unit min max 21 data-in setup time to stbi low 0 e ns 22 data-in hold time to stbi high 2.5 t3 e clk 23 stbi pulse width 1.5 e clk 24 stbo pulse width 1 clk 5ns e ns 25 data-out setup time to stbo low 2 e clk 26 data-out hold time from stbo high 5 e clk 27 stbi low to stbo low (rx interlock) e 2 clk 28 stbi low to stbo high (tx interlock) 2 e clk 29 data-in setup time to clock low 15 e ns 30 data-in hold time from clock low 7.5 e ns 31 clock high to data-out valid (cpu writes data, control, or direction) e 25 ns t3 = specification 23 64/96 tspc860 figure 43 : pip rx (interlock mode) timing diagram 21 23 24 22 data in 27 stbi stbo figure 44 : pip tx (interlock mode) timing diagram 25 23 28 24 (output) (input) 26 data out stbo stbi tspc860 65/96 figure 45 : pip rx (pulse mode) timing diagram 21 22 23 24 (input) (output) data in stbi stbo figure 46 : pip tx (pulse mode) timing diagram 25 26 24 23 (input) (output) data out stbo stbi 66/96 tspc860 figure 47 : parallel i/o data-in/data-out timing diagram clko data in data out 29 30 31 5.2. idma controller ac electrical specifications num characteristic all frequencies unit min max 40 dreq setup time to clock high 7 e ns 41 dreq hold time from clock high 3 e ns 42 sdack assertion delay from clock high e 12 ns 43 sdack negation delay from clock low e 12 ns 44 sdack negation delay from ta low e 20 ns 45 sdack negation delay from clock high e 15 ns 46 ta assertion to falling edge of the clock setup time * 7 e ns * applies to external ta. tspc860 67/96 figure 48 : idma external requests timing diagram 40 41 clko dreq (output) (input) figure 49 : sdack timing diagramperipheral write, ta sampled low at the falling edge of the clock sdack clko ts (output) rd / wr (output) data ta (output) 42 43 46 (output) 68/96 tspc860 figure 50 : sdack timing diagramperipheral write, ta sampled high at the falling edge of the clock sdack clko ts (output) rd / wr (output) data ta (output) 42 44 (output) tspc860 69/96 figure 51 : sdack timing diagramperipheral read sdack clko ts (output) rd / wr (output) data ta (output) 42 45 (output) 5.3. baud rate generator ac electrical specifications num characteristic all frequencies unit min max 50 brgo rise and fall time e 10 ns 51 brgo duty cycle 40 60 % 52 brgo cycle 40 e ns figure 52 : baud rate generator timing diagram 51 51 brgox 52 50 50 70/96 tspc860 5.4. timer ac electrical specifications num characteristic all frequencies unit min max 61 tin/tgate rise and fall time 10 e ns 62 tin/tgate low time 1 e clk 63 tin/tgate high time 2 e clk 64 tin/tgate cycle time 3 e clk 65 clko high to tout valid 3 25 ns figure 53 : cpm general-purpose timers timing diagram clko 60 61 61 65 63 62 64 tin / tgate (input) tout (output) tspc860 71/96 5.5. serial interface ac electrical specifications num characteristic all frequencies unit min max 70 l1rclk, l1tclk frequency (dsc=0) 1 3 e syncclk/2.5 mhz 71 l1rclk, l1tclk width low (dsc=0) 3 p+10 ns 71a l1rclk, l1tclk width high (dsc=0) 2 p+10 e ns 72 l1txd, l1st(14), l1rq, l1clko rise/fall time e 15 ns 73 l1rsync, l1tsync valid to l1clk edge (sync setup time) 20 e ns 74 l1clk edge to l1rsync, l1tsync invalid (sync hold time) 35 e ns 75 l1rsync, l1tsync rise/fall time e 15 ns 76 l1rxd valid to l1clk edge (l1rxd setup time) 17 e ns 77 l1clk edge to l1rxd invalid (l1rxd hold time) 13 e ns 78 l1clk edge to l1st(14) valid 10 45 ns 78a l1sync valid to l1st(14) valid 4 10 45 ns 79 l1clk edge to l1st(14) invalid 10 45 ns 80 l1clk edge to l1txd valid 10 55 ns 80a l1tsync valid to l1txd valid 4 10 55 ns 81 l1clk edge to l1txd high impedance 0 42 ns 82 l1rclk, l1tclk frequency (dsc=1) e 16 or syncclk/2 mhz 83 l1rclk, l1tclk width low (dsc=1) p+10 e ns 83a l1rclk, l1tclk width high (dsc=1) 2 p+10 e ns 72/96 tspc860 max min 84 l1clk edge to l1clko valid (dsc=1) e 30 ns 85 l1rq valid before falling edge of l1tsync 4 1 e l1tclk 86 l1gr setup time (see note 3) 42 e ns 87 l1gr hold time 42 e ns 88 l1clk edge to l1sync valid (fsd = 00, cnt = 0000, byt = 0, dsc=0) e 0 ns 1. the ratio syncclk/l1rclk must be greater than 2.5/1. 2. where p=1/clko1. thus for a 25 mhz clko1 rate, p= 40 ns. 3. these specs are valid for idl mode only. 4. the strobes and txd on the first bit of the frame becomes valid after l1clk edge or l1sync, whichever is later. figure 54 : si receive timing diagram with normal clocking (dsc =0) bit0 70 75 72 73 74 76 77 71 78 79 rfcd=1 l1rclk (fe=0, ce=0) (input) l1rclk (fe=1, ce=1) (input) l1rsync (input) l1rxd (input) l1st(14) (output) tspc860 73/96 figure 55 : si transmit timing diagram 70 75 72 73 74 71 79 tfcd=0 l1tclk (fe=0, ce=0) (input) l1tclk (fe=1, ce=1) (input) l1tsync (input) l1txd (output) l1st(14) (output) 80a bit0 80 78 81 78a figure 56 : si transmit timing with double speed clocking (dsc = 1) 74/96 tspc860 figure 57 : idl timing tspc860 75/96 5.6. scc in nmsi modeexternal clock electrical specifications the electrical specifications in this document are preliminary. num characteristic 40 mhz / 50 mhz unit min max 100 rclk1 and tclk1 width high 16 1/syncclk e ns 101 rclk1 and tclk1 width low 1/syncclk+5 e ns 102 rclk1 and tclk1 rise/fall time e 15 ns 103 txd1 active delay (from tclk1 falling edge) 0 50 ns 104 rts1 active/inactive delay (from tclk1 falling edge) 0 50 ns 105 cts1 setup time to tclk1 rising edge 5 e ns 106 rxd1 setup time to rclk1 rising edge 5 e ns 107 rxd1 hold time from rclk1 rising edge 2 5 e ns 108 cd1 setup time to rclk1 rising edge 5 e ns 1. the ratio syncclk/rclk1 and syncclk/tclk1 must be greater or equal to 2.25/1. 2. also applies to cd and cts hold time when they are used as an external sync signals. 76/96 tspc860 5.7. scc in nmsi modeinternal clock electrical specifications the electrical specifications in this document are preliminary. table 13 : nmsi external clock timing num characteristic all frequencies unit min max 100 rclk1 and tclk1 0 synoclk/3 mhz 102 rclk1 and tclk1 rise/fall time e e ns 103 txd1 active delay (from tclk1 falling edge) 0 30 ns 104 rts1 active/inactive delay (from tclk1 falling edge) 0 30 ns 105 cts1 setup time to tclk1 rising edge 40 e ns 106 rxd1 setup time to rclk1 rising edge 40 e ns 107 rxd1 hold time from rclk1 rising edge 2 0 e ns 108 cd1 setup time to rclk1 rising edge 40 e ns 1. the ratio syncclk/rclk1 and syncclk/tclk1 must be greater or equal to 3/1 2. also applies to cd and cts hold time when they are used as an external sync signals. tspc860 77/96 table 14 : nmsi internal clock timing num characteristic all frequencies unit min max 100 rclk1 and tclk1width high 1 1 /syncclk ns 101 rclk1 and tclk1width low 1/ syncclk +5 15 ns 102 rclk1 and tclk1 rise/fall time e e ns 103 txd1 active delay (from tclk1 falling edge) 0 50 ns 104 rts1 active/inactive delay (from tclk1 falling edge) 0 50 ns 105 cts1 setup time to tclk1 rising edge 5 e ns 106 rxd1 setup time to rclk1 rising edge 5 e ns 107 rxd1 hold time from rclk1 rising edge 2 5 e ns 108 cd1 setup time to rclk1 rising edge 5 e ns 1. the ratio syncclk/rclk1 and syncclk/tclk1 must be greater or equal to 2.25/1 2. also applies to cd and cts hold time when they are used as an external sync signals. 78/96 tspc860 figure 58 : scc nmsi receive timing diagram 101 100 107 108 106 rclk1 rxd1 107 cd1 (input) cd1 (sync input) 102 102 (input) figure 59 : scc nmsi transmit timing diagram 100 107 105 tclk1 txd1 103 104 104 rts1 cts1 cts1 (sync input) 102 102 101 (output) (output) (input) tspc860 79/96 figure 60 : hdlc bus timing diagram 100 105 tclk1 txd1 103 104 104 rts1 102 102 101 cts1 (echo 107 (output) (output) input 80/96 tspc860 5.8. ethernet electrical specifications num characteristic all frequencies unit min max 120 clsn width high 40 e ns 121 rclk1 rise/fall time e 15 ns 122 rclk1 width low 40 e ns 123 rclk1 clock period (see note 1) 80 120 ns 124 rxd1 setup time 20 e ns 125 rxd1 hold time 5 e ns 126 rena active delay (from rclk1 rising edge of the last data bit) 10 e ns 127 rena width low 100 e ns 128 tclk1 rise/fall time e 15 ns 129 tclk1 width low 40 e ns 130 tclk1 clock period (see note 1) 99 101 ns 131 txd1 active delay (from tclk1 rising edge) 10 50 ns 132 txd1 inactive delay (from tclk1 rising edge) 10 50 ns 133 tena active delay (from tclk1 rising edge) 10 50 ns 134 tena inactive delay (from tclk1 rising edge) 10 50 ns 135 rstrt active delay (from tclk1 falling edge) 10 50 ns 136 rstrt inactive delay (from tclk1 falling edge) 10 50 ns 137 reject width low 1 e clk 138 clko1 low to sdack asserted (see note 2) e 20 ns 139 clko1 low to sdack negated (see note 2) e 20 ns notes : 1. the ratio syncclk/rclk1 and syncclk/tclk1 must be greater or equal to 2/1 2. sdack is asserted whenever the sdma writes the incoming frame da into memory.1. tspc860 81/96 figure 61 : ethernet collision timing diagram 120 clsn(cts1) (input) figure 62 : ethernet receive timing diagram rclk1 rxd1 rena (cd1) (input) (input) 121 124 125 127 123 126 last bit 121 82/96 tspc860 figure 63 : ethernet transmit timing diagram 128 121 132 131 133 134 129 tclk1 txd1 rena (cd1) (input) (output) tena (rts1) (input) (note 2) 128 notes : 1. transmit clock invert (tci) bit in gsmr is set. 2. if rena is deasserted before tena, or rena is not asserted at all during transmit, then the csl bit is set in the buffer descriptor at the end of the frame transmission. figure 64 : cam interface receive start timing diagram 0 1 1 bit #1 bit #2 start frame delimiter 125 136 rclk1 rxd1 rstrt (output) (input) figure 65 : cam interface reject timing diagram 137 tspc860 83/96 5.9. i 2 c ac electrical specificationsscl < 100 kh z num characteristic all frequencies unit min max 150 clk1 clock period * 100 e ns 151 clk1 width low 50 e ns 151a clk1 width high 50 e ns 152 clk1 rise/fall time e 15 ns 153 txd1 active delay (from clk1 falling edge) 10 50 ns 154 rxd1/sync1 setup time 20 e ns 155 rxd1/sync1 hold time 5 e ns note : * the ratio syncclk/smclk must be greater or equal to 2/1. figure 66 : smc transparent timing diagram 150 151 151a 152 154 155 155 153 note 1 note:1.this delay is equal to an integer number of ocharacter lengtho clocks smclk txd1 (output) sync1 rxd1 (input) 152 154 84/96 tspc860 5.10. spi master ac electrical specifications num characteristic all frequencies unit min max 160 master cycle time 4 1024 tcyc 161 master clock (sck) high or low time 2 512 tcyc 162 master data setup time (inputs) 50 e ns 163 master data hold time (inputs) 0 e ns 164 master data valid (after sck edge) e 20 ns 165 master data hold time (outputs) 0 e ns 166 rise time output e 15 ns 167 fall time output e 15 ns figure 67 : spi master (cp=0) timing diagram spiclk ci=0 spiclk ci=1 msb in data lsbin msbin 162 167 163 165 164 166 166 167 167 166 161 msb out data lsb out msbout 160 161 output output input spimiso spimosi output tspc860 85/96 figure 68 : spi master (cp=1) timing diagram spiclk ci=0 spiclk ci=1 162 167 163 165 164 166 166 167 167 166 161 160 161 msb in data lsbin msbin msb out data lsb out msbout output output spimiso input spimosi input 86/96 tspc860 5.11. spi slave ac electrical specifications num characteristic all frequencies unit min max 170 slave cycle time 2 e tcyc 171 slave enable lead time 15 e ns 172 slave enable lag time 15 e ns 173 slave clock (spiclk) high or low time 1 e tcyc 174 slave sequential transfer delay (does not require deselect) 1 e tcyc 175 slave data setup time (inputs) 20 e ns 176 slave data hold time (inputs) 20 e ns 177 slave access time e 50 ns tspc860 87/96 figure 69 : spi slave (cp=0) timing diagram spiclk ci=0 spiclk ci=1 181 182 181 173 170 173 177 180 181 182 178 179 175 176 182 171 172 174 spisel input data data undef lsb in msb in msb out lsb out msb in msb out input spimosi input input output spimiso 33 figure 70 : spi slave (cp=1) timing diagram spiclk ci=0 spiclk ci=1 undef 170 174 172 182 181 173 173 171 181 177 179 178 182 180 175 176 181 182 spisel input input input spimiso output spimosi input data data lsbin lsbout msbin msbout msbin msbout 88/96 tspc860 5.12. i 2 c ac electrical specificationsscl < 100 kh z num characteristic all frequencies unit min max 200 scl clock frequency (slave) 0 100 khz 200 scl clock frequency (master) * 1.5 100 khz 202 bus free time between transmissions 4.7 e m s 203 low period of scl 4.7 e m s 204 high period of scl 4.0 e m s 205 start condition setup time 4.7 e m s 206 start condition hold time 4.0 e m s 207 data hold time 0 e m s 208 data setup time 250 e ns 209 sdl/scl rise time e 1 m s 210 sdl/scl fall time e 300 ns 211 stop condition setup time 4.7 e m s note : * scl frequency is given by scl = brgclk_frequency / ((brg register + 3) * pre_scaler * 2). the ratio syncclk/(brgclk/pre_scaler) must be greater or equal to 4/1. tspc860 89/96 5.13. i 2 c ac electrical specificationsscl > 100 kh z num characteristic expression min max unit 200 scl clock frequency (slave) fscl 0 brgclk/48 hz 200 scl clock frequency (master) * fscl brgclk/16512 brgclk/48 hz 202 bus free time between transmissions 1/(2.2 * fscl) e s 203 low period of scl 1/(2.2 * fscl) e s 204 high period of scl 1/(2.2 * fscl) e s 205 start condition setup time 1/(2.2 * fscl) e s 206 start condition hold time 1/(2.2 * fscl) e s 207 data hold time 0 e s 208 data setup time 1/(40 * fscl) e s 209 sdl/scl rise time e 1/(10 * fscl) s 210 sdl/scl fall time e 1/(33 * fscl) s 211 stop condition setup time 1/(2.2 * fscl) e s note : * scl frequency is given by scl = brgclk_frequency / ((brg register + 3) * pre_scaler * 2). the ratio syncclk/(brg_clk/pre_scaler) must be greater or equal to 4/1. figure 71 : i 2 c bus timing diagram 202 sda scl 203 204 205 207 208 209 206 210 211 90/96 tspc860 6. preparation for delivery 6.1. packaging microcircuits are prepared for delivery in accordance with mil-prf-38535. 6.2. certificate of compliance atmel-grenoble offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with mil-std-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. 7. power consideration the average chip-junction temperature, tj, in c can be obtained from the equation : tj = t a + (p d ja ) (1) where t a = ambient temperature, c ja = package thermal resistance, junction to ambient, c/w p d = p int + p i/o p int = i dd x v dd , watts - chip internal power p i/o = power dissipation on input and output pins - user determined for most applications p i/o < 0.3 p int and can be neglected. if p i/o is neglected, an approximate relationship between p d and t j is : p d = k (t j + 273 c)(2) solving equations (1) and (2) for k gives : k= p d ? t (t a + 273 c) + ja p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . 8. layout practices each v cc pin on the tspc860 should be provided with a low-impedance path to the board's supply. each gnd pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v cc power supply should be bypassed to ground using at least four 0.1 f by-pass capacitors located as close as possible to the four sides of the pac- kage. the capacitor leads and associated printed circuit traces connecting to chip v cc and gnd should be kept to less than half an inch per capacitor lead. a four-layer board is recommended, employing two inner layers as v cc and gnd planes. all output pins on the tsppc860 have fast rise and fall times. printed circuit (pc) trace interconnection length should be mini mized in order to minimize undershoot and reflections caused by these fast output switching times. this recommendation particularly appl ies to the address and data busses. maximum pc trace lengths of six inches are recommended. capacitance calculations should con- sider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing bec omes especially critical in systems with higher capacitive loads because these loads create higher transient current in the v cc and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the n oise levels on the pll supply pins. 9. functional units description the tspc860 powerquicc integrates the embedded powerpc core with high performance, low power peripherals to extend the motorola data communications family of embedded processors even farther into high end communications and networking prod- ucts. the tspc860 powerquicc is comprised of three modules which all use the 32-bit internal bus : the embedded powerpc core, the system integration unit (siu), and the communication processor module (cpm). the tspc860 powerquicc block diagram is shown in figure 1. tspc860 91/96 9.1. embedded powerpc core the embedded powerpc core is compliant with the book 1 specification for the powerpc architecture. the embedded powerpc core is a fully static design that consists of two functional blocks ; the integer block and the load/store block. it executes all integer and load/store operations directly on the hardware. the core supports integer operations on a 32-bit internal data path and 32-bit arithme- tic hardware. the core interface to the internal and external buses is 32 bits. the core uses a two instruction load/store queu e, a four instruction prefetch queue, and a six instruction history buffer. the core does branch folding and branch prediction with condi tional pre-fetch but without conditional execution. the embedded powerpc core can operate on 32-bit external operands with one bus cycle. the powerpc integer block supports 32 x 32-bit fixed point general purpose registers. it can execute one integer instruction ea ch clock cycle. each element in the integer block is clocked only when valid data is present in the data queue ready for operation . this assures that the power consumption of the device is held to the absolute minimum required to perform an operation. the embedded powerpc core is integrated with mmu's as well as 4 kbyte instruction and data caches. each mmu provides a 32 entry, fully associative instruction and data tlb, with multiple page sizes of : 4 kb, 16 kb, 512kb, 256 kb and 8 mb. it will s upport 16 virtual address spaces with 8 protection groups. three special registers are available as scratch registers to support software table walk and update. the instruction cache is 4 kilobytes, two-way, set associative with physical addressing. it allows single cycl e access on hit with no added latency for miss. it has four words per line, supporting burst line fill using least recently used (lru) r eplacement. the cache can be locked on a per line basis for application critical routines. the data cache is 4 kilobytes, two-way, set associative with physical addressing. it allows single cycle access on hit with one added clock latency for miss. it has four words per line, supporting burst line fill using lru replacement. the cache can be locked o n a per line basis for application critical routines. the data cache can be programmed to support copy-back or write-through via the mm u. the inhibit mode can be programmed per mmu page. the embedded powerpc core with its instruction and data caches delivers approximately 52 mips at 40 mhz, using dhrystone 2.1, based on the assumption that it is issuing one instruction per cycle with a cache hit rate of 94 %. the embedded powerpc core contains a much improved debug interface that provides superior debug capabilities without causing any degradation in the speed of operation. this interface supports six watchpoint pins that are used to detect software events. inter- nally it has eight comparators, four of which operate on the effective address on the address bus. the remaining four comparato rs are split, with two comparators the effective address on the data bus, and two comparators operating on the data on the data bus. t he embedded powerpc core can compare using =, , <, > conditions to generate watchpoints. each watchpoint can then generate a breakpoint that can be programmed to trigger in a programmable number of events. 9.2. system interface unit (siu) the siu on the tspc860 powerquicc integrates general-purpose features useful in almost any 32-bit processor system, enhanc- ing the performance provided by the system integration module (sim) on the ts68en360 quicc device. although the embedded powerpc core is always a 32-bit device internally, it may be configured to operate with an 8-, 16- or 32- bit data bus. regardless of the choice of the system bus size, dynamic bus sizing is supported. bus sizing allows 8-, 16-, and 32-b it peripherals and memory to exist in the 32-bit system bus mode. the siu also provides power management functions, reset control, powerpc decrementer, powerpc time base and powerpc real time clock. the memory controller will support up to eight memory banks with glueless interfaces to dram, sram, ssram, eprom, flash eprom, srdram, edo and other peripherals with two-clock access to external sram and bursting support. it provides variable block sizes from 32 kilobytes to 256 megabytes. the memory controller will provide 0 to 15 wait states for each bank of memory and can use address type matching to qualify each memory bank access. it provides four byte enable signals for varying width de vi- ces, one output enable signal and one boot chip select available at reset. the dram interface supports port sizes of 8, 16, and 32 bits. memory banks can be defined in depths of 256k, 512k, 1m, 2m, 4m, 8m, 16m, 32m, or 64m for all port sizes. in addition the memory depth can be defined as 64k and 128k for 8-bit memory or 128m and 2 56m for 32-bit memory. the dram controller supports page mode access for successive transfers within bursts. the tspc860 will sup- port a glueless interface to one bank of dram while external buffers are required for additional memory banks. the refresh unit pro- vides cas before ras, a programmable refresh timer, refresh active during external reset, disable refresh modes, and stacking u p to 7 refresh cycles. the dram interface uses a programmable state machine to support almost any memory interface. 9.2.1.pcmcia controller the pcmcia interface is a master (socket) controller and is compliant with release 2.1. the interface will support up to two in depen- dent pcmcia sockets requiring only external transceivers/buffers. the interface provides 8 memory or i/o windows where each win - dow can be allocated to a particular socket. if only one pcmcia port is being used, the unused pcmcia port may be used as gener al- purpose input with interrupt capability. 92/96 tspc860 9.2.2.power management the tspc860 powerquicc supports a wide range of power management features including full on, doze, sleep, deep sleep, and low power stop. in full on mode the tspc860 processor is fully powered with all internal units operating at the full speed of t he processor. a gear mode is provided which is determinated by a clock divider, allowing the os to reduce the operational frequenc y of the processor. doze mode disables core functional units other than the time base decrementer, pll, memory controller, rtc, and then places the cpm in low power standby mode. sleep mode disables everything except the rtc and pit, leaving the pll for lower power but slower wake-up. low power stop disables all logic in the processor except the minimum logic required to restart the d evice, providing the lowest power consumption but requiring the longest wake-up time. 9.2.3.communications processor module (cpm) the tspc860 powerquicc is the next generation ts68en360 quicc and like its predecessor implements a dual processor archi- tecture. this dual processor architecture provides both a high performance general purpose processor for application programmin g use as well as a special purpose communication processor (cpm) uniquely designed for communications needs. the cpm contains features that allow the tspc860 powerquicc to excel in communications and networking products as did the ts68en360 quicc which prededed it. these features may be divided into three sub-groups : . communications processor (cp) . sixteen independent dma (sdma) controllers . four general-purpose timers the cp provides the communication features of the tspc860 powerquicc. included are a risc processor, four serial communica- tion controllers (scc) four serial management controllers (smc), one serial peripheral interface (spi), one i 2 interface , 5 kilobytes of dual-port ram, an interrupt controller, a time slot assigner, three parallel ports, a parallel interface port, four independ ent baud rate generators, and sixteen serial dma channels to support the sccs, smcs, spi, and i 2 c. the sdmas provide two channels of general-purpose dma capability for each communications channel. they offer high-speed transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge logic. the four general-purpose timers on the cpm are identical to the timers found on the mc68360 and still support the internal casc ading of two timers to form a 32-bit timer. the tspc860 powerquicc maintains the best features of the ts68en360 quicc, while making changes required to provide for the increased flexibility, integration, and performance requested by customers demanding the performance of the powerpc archite c- ture. the addition of a multiply-and-accumulate (mac) function on the cpm further enhances the tspc860 powerquicc, enabling various modem and dsp applications. because the cpm architectural approach remains intact between the tspc860 powerquicc and the ts68en360 quicc, a user of the ts68en360 quicc can easily become familiar with the tspc860 powerquicc. 9.3. software compatibility issues the following list summarizes the major software differences between the ts68en360 quicc and the tspc860 powerquicc : since the tspc860 powerquicc uses an embedded powerpc core, code written for the ts68en360 must be recompiled for the powerpc instruction set. code which accesses the ts68en360 peripherals requires only minor modifications for use with the tspc860. although the functions performed by the powerquicc siu are similar to those performed by the quicc sim, the initialization sequence for the siu is different and therefore code that accesses the siu must be rewritten. many developers of 68k compilers now provide compilers which also support the powerpc architecture. the addition of the mac function to the tspc860 cpm block to support the needs of higher performance communication software is the only major difference between the cpm on the ts68en360 and that on the tspc860. therefore the registers used to initial- ize the quicc cpm are similar to the tspc860 cpm, but there are some minor changes necessary for supporting the mac func- tion. when porting code from the ts68en360 cpm to the tspc860 cpm, the software writer will find new options for hardware break- point on cpu commands, address, and serial request which are useful for software debugging. support for single step operation with all the registers of the cpm visible makes software development for the cpm on the tspc860 processor even simpler. tspc860 93/96 9.4. tspc860 powerquicc glueless system design a fundamental design goal of the tspc860 powerquicc was ease of interface to other system components. figure 72 shows a system configuration that offers one eprom, one flash eprom, and supports two dram simms. depending on the capacitance on the system bus, external buffers may be required. from a logic standpoint, however, a glueless system is maintained. figure 72 : tspc860 system configuration 10. handling mos devices must be handled with certain precautions to avoid damage due to accumulation of static charge. input protection dev i- ces have been designed in the chip to minimize the effect of this static buildup. however, the following handling practices are recom- mended : a) devices should be handled on benches with conductive and grounded surfaces. b) ground test equipment, tools and operator. c) do not handle devices by the leads. d) store devices in conductive foam or carriers. e) avoid use of plastic, rubber, or silk in mos areas. f) maintain relative humidity above 50 percent if practical. 94/96 tspc860 11. package dimensions 11.1. plastic ball grid array dim min max millimeters a 2.05 a1 0.50 0.70 a2 0.95 1.35 a3 0.70 0.90 b 0.60 0.90 d 25.00 bsc d1 22.86 bsc d2 22.40 22.60 e 25.00 bsc e1 22.86 bsc e2 e 1.27 bsc notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b is the solder ball diameter measured parallel to datum c. d 0.20 a e e1 0.25 c 0.20 c d2 top view e2 a2 a1 bottom view a3 b 18x 4x d1 e b 12345678910111213141516 a b c d e f g h j k l m n p r t 0.03 c a b 0.15 c a 0.35 c c side view 22.40 22.60 19 18 17 u v w m m 357x tspc860 95/96 12. definitions datasheet status validity objective specification this datasheet contains target and goal specifi- cation for discussion with customer and applica- tion validation. before design phase. target specification this datasheet contains target or goal specifica- tion for product development. valid during the design phase. preliminary specification site this datasheet contains preliminary data. addi- tional data may be published later ; could include simulation result. valid before characteriza- tion phase. preliminary specification site this datasheet contains also characterization results. valid before the industrial- ization phase. product specification this datasheet contains final product specifica- tion. valid for production pur- pose. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. atmel-grenoble customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify atmel-grenoble for any dam- ages resulting from such improper use or sale. 96/96 tspc860 13. ordering information prototype temperature range : t c pc860 zp u 40 m : -55, +125 c v : -40, +110 c ts prefix (1) (x) type (1) for availability of the different versions, contact your atmel-grenoble sale office m screening leve l (2) zp : pbga max internal processor speed (1) 40 : 40 mhz 50 : 50 mhz __ : standard u : upscreening u/t : upscreening + burn-in c mh version revision level b: rev b. 0 (mh version) c: rev c.1 (mh version) package mh: ethernet support sr: ethernet and atm support d: rev d.4 (sr version) 66 : 66 mhz (sr only) 80 : 80 mhz (sr only) tbc 4. information furnished is believed to be accurate and reliable. however atmel-grenoble assumes no responsibility for the conse- quences of use of such information nor for any infringement of patents or other rights of third parties which may result from i ts use. no license is granted by implication or otherwise under any patent or patent rights of atmel-grenoble. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. atmel- grenoble products are not authorized for use as critical components in life support devices or systems without express written approval from atmel-grenoble. ? 2000 atmel-grenoble- printed in france - all rights reserved. this product is manufactured by atmel-grenoble- 38521 saint-egreve - france. for further information please contact : atmel-grenoble - route dpartementale 128 - b.p. 46 - 91401 orsay cedex - france - phone +33 (0)1 69 33 00 00 - fax +33 (0)1 69 33 03 21. internet:http://www.atmel-grenoble.com |
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